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mx.microsoft.com 1; spf=pass smtp.mailfrom=citrix.com; dmarc=pass action=none header.from=citrix.com; dkim=pass header.d=citrix.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=citrix.onmicrosoft.com; s=selector2-citrix-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=ea2OyWmpWeWANsLogJ31RjsyaXJdLUB3QXTZ/zC3WVM=; b=gZRllac2G+iqsgaFzBQr92epK8lM6BuOr04NP8Q3fItq4BYPB5BBfOPxkxrWH7nOY5p0LxDhybl4KqtFTreURxdSZhM1pPrvFEK8JyrefozLEow+xpXjJS0Cgu/T6UPZeq+pixANIrSZbuAN5WUbhOwYYAC5eE/UW+eBuGVC1xk= From: Roger Pau Monne To: CC: Andrew Cooper , Roger Pau Monne , Ian Jackson , Wei Liu Subject: [PATCH v3 09/13] libs/guest: introduce helper set cpu topology in cpu policy Date: Fri, 30 Apr 2021 17:52:07 +0200 Message-ID: <20210430155211.3709-10-roger.pau@citrix.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210430155211.3709-1-roger.pau@citrix.com> References: <20210430155211.3709-1-roger.pau@citrix.com> X-ClientProxiedBy: MRXP264CA0010.FRAP264.PROD.OUTLOOK.COM (2603:10a6:500:15::22) To DS7PR03MB5608.namprd03.prod.outlook.com (2603:10b6:5:2c9::18) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 7f7c8eed-39a8-401e-6040-08d90bf03baf X-MS-TrafficTypeDiagnostic: DM6PR03MB4218: X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:1169; 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X-MS-Exchange-AntiSpam-MessageData: =?utf-8?q?9Sz2otTxCGftmdnDarP/GLcBRApM7Z?= =?utf-8?q?i0oCMTVVxgKAIGhLYxn758mdeTIy63wfZqKGjLFxhUYvPosV4B64nfhqt5KJWUN8e?= =?utf-8?q?XLvrBwFFWU3g5MAkwozHXS3lOsAITjtWvwI8yhvQliLKRFdKMfTV+3j/B0iwfS0rk?= =?utf-8?q?O1tAIpczQoNadlXlsiZv7UdKvfcr+BGiVqih1CFO8ZKuVg2zdthpHJIAIv8OJ2TcN?= =?utf-8?q?Z6+0gWkhNwlsXQjFvriyuxXz/B/vKTaPflxTfBGW7AwSc839OU4jja0ZHxbzdICLN?= =?utf-8?q?uLaKcr4bleMJxDJEwwBKrqWx1JRaERUno2qD/OIt0l/GhYizJHwqkXFCDW+b83fuv?= =?utf-8?q?xgHYlDvNn0F6NeT1yHBeEVBb53K3uIceNIu2YvAicCSNwhw5SeSf9UU2ZB6dEICym?= =?utf-8?q?9VeBYXZf+RUjO27vIy2m1UJnpFfD6pwwlOz4TWFxtLDIF2+992BV4r50mJlcJ9CV6?= =?utf-8?q?Tc2nHOKAU/J4Z+rln7eW96aBmxxPpayFi62mHsnUHoF9ncSo4kdEo854FAe/pG9Ch?= =?utf-8?q?vb42pxtd6uZMaJgLIR7+3JeM5dFHE2WEFLOWyq0dj2bk/67ArWXKQkYcBJfoVSFgz?= =?utf-8?q?FdIHffyTLZpQNARbbyWRlxsMoYSBP5tuvMyJwLHBjg8EjZe6gPs34OTdAIHGsgRk8?= =?utf-8?q?l/frEL9SmUCV5j/KCxTq6IlX27I5kjFFbG0CuGU8hQvraDljgF2JlV4TfmSwZwmSN?= =?utf-8?q?IgtNgADAywuigtzzAFd+juh0vXUCitxrO4HTcwUMwTxc4ceer8SeQKMPjXEY419YV?= =?utf-8?q?ZY7YllVjcHClyX4NODK5ZbBBmLd5umQ+zrYjSpPKSJDL1ntBtPMqrG4Bn2i/hCSin?= =?utf-8?q?7gbZKMfvhrjRPd6kXEiDMBbiT1e5UNMoEfj4KpsKDPhWBKIFX2kq7S1ohhE+JO4CO?= =?utf-8?q?be/bfWtmuODbBhfEXN+AZ/ML270fhJ4rHP+/b3KOQWMSss9ezGtI7ngtGuh7vdTSV?= =?utf-8?q?Sbs88Ad1qNe3b4TE82V/SUqu0XOjJ0hO6Nf64V248iegtEmcGKN1or66w6DvyTXyN?= =?utf-8?q?WTtaT68UZ8fHpUGc3IzEw8XXqp7xxrBo4cbUaz84E6kwHENQppcdC7PBsji2eGO1v?= =?utf-8?q?P109NgyucBsIiGnErPAH1ci6mycxruQV0GqyZ4YOKnze9ZXJriffzrnB/xPNgWk3H?= =?utf-8?q?EjitEkeVCTRziDCCqQAnC+tc3BMjWSQR2+aOdYOmkwkA7/Q3XnO+w100JrwEkA02w?= =?utf-8?q?5ySVAyVs2KNVFWNkatMDTlJgoTdrXP98xv+on56vsVTEB4LXrBVsmywcJNEPY84qS?= =?utf-8?q?GUJQq7KL7gw3EF?= X-MS-Exchange-CrossTenant-Network-Message-Id: 7f7c8eed-39a8-401e-6040-08d90bf03baf X-MS-Exchange-CrossTenant-AuthSource: DS7PR03MB5608.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Apr 2021 15:54:27.2096 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 335836de-42ef-43a2-b145-348c2ee9ca5b X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: lkTcfXjmbOjQnbRFG93ULT3/UUBR0LP3EzrhzTqFMS/EtciQAV4pgPZ5H31RWkPaL/j96kupHIJcLouh4SE0Jw== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR03MB4218 X-OriginatorOrg: citrix.com This logic is pulled out from xc_cpuid_apply_policy and placed into a separate helper. Note the legacy part of the introduced function, as long term Xen will require a proper topology setter function capable of expressing a more diverse set of topologies. No functional change intended. Signed-off-by: Roger Pau Monné --- - s/xc_cpu_policy_topology/xc_cpu_policy_legacy_topology/ --- tools/include/xenctrl.h | 4 + tools/libs/guest/xg_cpuid_x86.c | 182 +++++++++++++++++--------------- 2 files changed, 103 insertions(+), 83 deletions(-) diff --git a/tools/include/xenctrl.h b/tools/include/xenctrl.h index 89a73fd6823..ec184bccd3f 100644 --- a/tools/include/xenctrl.h +++ b/tools/include/xenctrl.h @@ -2631,6 +2631,10 @@ int xc_cpu_policy_calc_compatible(xc_interface *xch, int xc_cpu_policy_make_compatible(xc_interface *xch, xc_cpu_policy_t policy, bool hvm); +/* Setup the legacy policy topology. */ +int xc_cpu_policy_legacy_topology(xc_interface *xch, xc_cpu_policy_t policy, + bool hvm); + int xc_get_cpu_levelling_caps(xc_interface *xch, uint32_t *caps); int xc_get_cpu_featureset(xc_interface *xch, uint32_t index, uint32_t *nr_features, uint32_t *featureset); diff --git a/tools/libs/guest/xg_cpuid_x86.c b/tools/libs/guest/xg_cpuid_x86.c index 855d252e067..dbf2ef67ee0 100644 --- a/tools/libs/guest/xg_cpuid_x86.c +++ b/tools/libs/guest/xg_cpuid_x86.c @@ -443,13 +443,11 @@ int xc_cpuid_apply_policy(xc_interface *xch, uint32_t domid, bool restore, { int rc; xc_dominfo_t di; - unsigned int i, nr_leaves, nr_msrs; + unsigned int nr_leaves, nr_msrs; xen_cpuid_leaf_t *leaves = NULL; struct cpuid_policy *p = NULL; struct xc_cpu_policy policy = { }; uint32_t err_leaf = -1, err_subleaf = -1, err_msr = -1; - uint32_t host_featureset[FEATURESET_NR_ENTRIES] = {}; - uint32_t len = ARRAY_SIZE(host_featureset); if ( xc_domain_getinfo(xch, domid, 1, &di) != 1 || di.domid != domid ) @@ -472,22 +470,6 @@ int xc_cpuid_apply_policy(xc_interface *xch, uint32_t domid, bool restore, (p = calloc(1, sizeof(*p))) == NULL ) goto out; - /* Get the host policy. */ - rc = xc_get_cpu_featureset(xch, XEN_SYSCTL_cpu_featureset_host, - &len, host_featureset); - if ( rc ) - { - /* Tolerate "buffer too small", as we've got the bits we need. */ - if ( errno == ENOBUFS ) - rc = 0; - else - { - PERROR("Failed to obtain host featureset"); - rc = -errno; - goto out; - } - } - /* Get the domain's default policy. */ nr_msrs = 0; rc = get_system_cpu_policy(xch, di.hvm ? XEN_SYSCTL_cpu_policy_hvm_default @@ -571,70 +553,11 @@ int xc_cpuid_apply_policy(xc_interface *xch, uint32_t domid, bool restore, } } - if ( !di.hvm ) - { - /* - * On hardware without CPUID Faulting, PV guests see real topology. - * As a consequence, they also need to see the host htt/cmp fields. - */ - p->basic.htt = test_bit(X86_FEATURE_HTT, host_featureset); - p->extd.cmp_legacy = test_bit(X86_FEATURE_CMP_LEGACY, host_featureset); - } - else - { - /* - * Topology for HVM guests is entirely controlled by Xen. For now, we - * hardcode APIC_ID = vcpu_id * 2 to give the illusion of no SMT. - */ - p->basic.htt = true; - p->extd.cmp_legacy = false; - - /* - * Leaf 1 EBX[23:16] is Maximum Logical Processors Per Package. - * Update to reflect vLAPIC_ID = vCPU_ID * 2, but make sure to avoid - * overflow. - */ - if ( !(p->basic.lppp & 0x80) ) - p->basic.lppp *= 2; - - switch ( p->x86_vendor ) - { - case X86_VENDOR_INTEL: - for ( i = 0; (p->cache.subleaf[i].type && - i < ARRAY_SIZE(p->cache.raw)); ++i ) - { - p->cache.subleaf[i].cores_per_package = - (p->cache.subleaf[i].cores_per_package << 1) | 1; - p->cache.subleaf[i].threads_per_cache = 0; - } - break; - - case X86_VENDOR_AMD: - case X86_VENDOR_HYGON: - /* - * Leaf 0x80000008 ECX[15:12] is ApicIdCoreSize. - * Leaf 0x80000008 ECX[7:0] is NumberOfCores (minus one). - * Update to reflect vLAPIC_ID = vCPU_ID * 2. But avoid - * - overflow, - * - going out of sync with leaf 1 EBX[23:16], - * - incrementing ApicIdCoreSize when it's zero (which changes the - * meaning of bits 7:0). - * - * UPDATE: I addition to avoiding overflow, some - * proprietary operating systems have trouble with - * apic_id_size values greater than 7. Limit the value to - * 7 for now. - */ - if ( p->extd.nc < 0x7f ) - { - if ( p->extd.apic_id_size != 0 && p->extd.apic_id_size < 0x7 ) - p->extd.apic_id_size++; - - p->extd.nc = (p->extd.nc << 1) | 1; - } - break; - } - } + policy.cpuid = *p; + rc = xc_cpu_policy_legacy_topology(xch, &policy, di.hvm); + if ( rc ) + goto out; + *p = policy.cpuid; rc = x86_cpuid_copy_to_buffer(p, leaves, &nr_leaves); if ( rc ) @@ -1114,3 +1037,96 @@ int xc_cpu_policy_make_compatible(xc_interface *xch, xc_cpu_policy_t policy, xc_cpu_policy_destroy(host); return rc; } + +int xc_cpu_policy_legacy_topology(xc_interface *xch, xc_cpu_policy_t policy, + bool hvm) +{ + if ( !hvm ) + { + xc_cpu_policy_t host; + int rc; + + host = xc_cpu_policy_init(); + if ( !host ) + { + errno = ENOMEM; + return -1; + } + + rc = xc_cpu_policy_get_system(xch, XEN_SYSCTL_cpu_policy_host, host); + if ( rc ) + { + ERROR("Failed to get host policy"); + xc_cpu_policy_destroy(host); + return rc; + } + + + /* + * On hardware without CPUID Faulting, PV guests see real topology. + * As a consequence, they also need to see the host htt/cmp fields. + */ + policy->cpuid.basic.htt = host->cpuid.basic.htt; + policy->cpuid.extd.cmp_legacy = host->cpuid.extd.cmp_legacy; + } + else + { + unsigned int i; + + /* + * Topology for HVM guests is entirely controlled by Xen. For now, we + * hardcode APIC_ID = vcpu_id * 2 to give the illusion of no SMT. + */ + policy->cpuid.basic.htt = true; + policy->cpuid.extd.cmp_legacy = false; + + /* + * Leaf 1 EBX[23:16] is Maximum Logical Processors Per Package. + * Update to reflect vLAPIC_ID = vCPU_ID * 2, but make sure to avoid + * overflow. + */ + if ( !(policy->cpuid.basic.lppp & 0x80) ) + policy->cpuid.basic.lppp *= 2; + + switch ( policy->cpuid.x86_vendor ) + { + case X86_VENDOR_INTEL: + for ( i = 0; (policy->cpuid.cache.subleaf[i].type && + i < ARRAY_SIZE(policy->cpuid.cache.raw)); ++i ) + { + policy->cpuid.cache.subleaf[i].cores_per_package = + (policy->cpuid.cache.subleaf[i].cores_per_package << 1) | 1; + policy->cpuid.cache.subleaf[i].threads_per_cache = 0; + } + break; + + case X86_VENDOR_AMD: + case X86_VENDOR_HYGON: + /* + * Leaf 0x80000008 ECX[15:12] is ApicIdCoreSize. + * Leaf 0x80000008 ECX[7:0] is NumberOfCores (minus one). + * Update to reflect vLAPIC_ID = vCPU_ID * 2. But avoid + * - overflow, + * - going out of sync with leaf 1 EBX[23:16], + * - incrementing ApicIdCoreSize when it's zero (which changes the + * meaning of bits 7:0). + * + * UPDATE: I addition to avoiding overflow, some + * proprietary operating systems have trouble with + * apic_id_size values greater than 7. Limit the value to + * 7 for now. + */ + if ( policy->cpuid.extd.nc < 0x7f ) + { + if ( policy->cpuid.extd.apic_id_size != 0 && + policy->cpuid.extd.apic_id_size < 0x7 ) + policy->cpuid.extd.apic_id_size++; + + policy->cpuid.extd.nc = (policy->cpuid.extd.nc << 1) | 1; + } + break; + } + } + + return 0; +}