From patchwork Thu Sep 2 16:15:31 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 12472069 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8E78CC87FC9 for ; Thu, 2 Sep 2021 16:30:57 +0000 (UTC) Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 6528961A4E for ; Thu, 2 Sep 2021 16:22:01 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 6528961A4E Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=amsat.org Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=lists.xenproject.org Received: from list by lists.xenproject.org with outflank-mailman.177522.323051 (Exim 4.92) (envelope-from ) id 1mLpTN-0006EG-Uq; Thu, 02 Sep 2021 16:21:53 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 177522.323051; Thu, 02 Sep 2021 16:21:53 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1mLpTN-0006Di-QM; Thu, 02 Sep 2021 16:21:53 +0000 Received: by outflank-mailman (input) for mailman id 177522; Thu, 02 Sep 2021 16:21:52 +0000 Received: from us1-rack-iad1.inumbo.com ([172.99.69.81]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1mLpPQ-00029c-RL for xen-devel@lists.xenproject.org; Thu, 02 Sep 2021 16:17:48 +0000 Received: from mail-wm1-x330.google.com (unknown [2a00:1450:4864:20::330]) by us1-rack-iad1.inumbo.com (Halon) with ESMTPS id 35337728-37d5-4f15-99e8-bf5d5c0bc7c4; Thu, 02 Sep 2021 16:17:42 +0000 (UTC) Received: by mail-wm1-x330.google.com with SMTP id k20-20020a05600c0b5400b002e87ad6956eso1752432wmr.1 for ; Thu, 02 Sep 2021 09:17:42 -0700 (PDT) Received: from x1w.. (163.red-83-52-55.dynamicip.rima-tde.net. [83.52.55.163]) by smtp.gmail.com with ESMTPSA id b10sm2396452wrt.43.2021.09.02.09.17.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 02 Sep 2021 09:17:41 -0700 (PDT) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list X-Inumbo-ID: 35337728-37d5-4f15-99e8-bf5d5c0bc7c4 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=zZDEgfpsGMQvs/Uf9L14U8iNfhU1RYAtDHEnPo7PYYM=; b=GULtcfLvxCYjpD88B1lNFiQq0+Fx5WhxaqykU8SQ2CHcFSQ46Oe+PaWfXkceFQ4mZo 9SVUhNZ9o3T9wPipJYMj4yipSNtMQdK9k6FheUrkcj3bklOdIm+96woKK1z756yLjsg/ MhcJnDjB6bDPTEVYbHN4OuhakMfbQHLPwIuQo7fhJI4LnxL+hhUixbbozhsjDk51Ju96 gEVW+K7GtzvK1ZSbUGOUZzNQwoBSJHeiBUhu/bkunqvaYTW0krBKCnLFihT41xPY7/te UIojuKoYb6sy0krnR6uivIpg05XXUq83++TFLX9QNOJMrVv7jBEaRQx/6ic9TCOEtLyT HNGQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=zZDEgfpsGMQvs/Uf9L14U8iNfhU1RYAtDHEnPo7PYYM=; b=s/ZlfdL2kPbg27cSacwE2l9+XTd6UgsmCFwLHqX5ZQEBOyLQZ/ih5yVl8LVtOJPBgY pHw6FDTkAyjPcQeCQcbneLIoxnPrTBswd8JJCWURFMLaFpQKDMlyE4lH6g9okWwlhge1 PK/9qqBIjHm70UUj8XTCI0Tll+XqFWPHLUonS2d2vGfK9Jh9GR0V6OhPtHSnc2kVYGk4 ouke6U000KZXsX9cDfD4101o8PlkaBRky+ahJZHOdB53WctZWPGLQIMJHADQtoVqPV0L ZC8iZdviq7Rhk1FxI+1BduhFztCxVXKGcWBeN8Nm7JcxgMieyL4ENl0N0dLivNDXWFjV oS9A== X-Gm-Message-State: AOAM532+81vKHQ8Y6U/8zPktKodLsiFSkERZsoIO4SC4OfAr9ikDjtKG oJlLu2QMYb9U2hSSP+Eps1s= X-Google-Smtp-Source: ABdhPJyVfC2B9mnkyBEM+dhp2QSoSDx2mJAJ4q0c4MKaFScZUxxMUDRDRaRsAykGgf3YQuNS/WTfdA== X-Received: by 2002:a05:600c:3641:: with SMTP id y1mr3991806wmq.181.1630599461974; Thu, 02 Sep 2021 09:17:41 -0700 (PDT) Sender: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Bin Meng , Eduardo Habkost , Greg Kurz , haxm-team@intel.com, Kamil Rytarowski , qemu-ppc@nongnu.org, Anthony Perard , Marcel Apfelbaum , Michael Rolnik , qemu-riscv@nongnu.org, Paolo Bonzini , Jiaxun Yang , Thomas Huth , David Hildenbrand , Chris Wulff , Laurent Vivier , Cameron Esfahani , Sunil Muthuswamy , Max Filippov , Taylor Simpson , qemu-s390x@nongnu.org, Richard Henderson , Bastian Koppelmann , Yoshinori Sato , Artyom Tarasenko , Aurelien Jarno , Paul Durrant , Peter Maydell , David Gibson , Alistair Francis , "Edgar E. Iglesias" , Roman Bolshakov , Laurent Vivier , Cornelia Huck , qemu-arm@nongnu.org, Wenchao Wang , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , xen-devel@lists.xenproject.org, Marek Vasut , Stefano Stabellini , Aleksandar Rikalo , Mark Cave-Ayland , Colin Xu , Claudio Fontana , Palmer Dabbelt , Stafford Horne , Reinoud Zandijk , kvm@vger.kernel.org Subject: [PATCH v3 18/30] target/nios2: Restrict has_work() handler to sysemu and TCG Date: Thu, 2 Sep 2021 18:15:31 +0200 Message-Id: <20210902161543.417092-19-f4bug@amsat.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210902161543.417092-1-f4bug@amsat.org> References: <20210902161543.417092-1-f4bug@amsat.org> MIME-Version: 1.0 Restrict has_work() to TCG sysemu. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- target/nios2/cpu.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/target/nios2/cpu.c b/target/nios2/cpu.c index 947bb09bc1e..f1f976bdad7 100644 --- a/target/nios2/cpu.c +++ b/target/nios2/cpu.c @@ -34,10 +34,12 @@ static void nios2_cpu_set_pc(CPUState *cs, vaddr value) env->regs[R_PC] = value; } +#if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY) static bool nios2_cpu_has_work(CPUState *cs) { return cs->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_NMI); } +#endif /* CONFIG_TCG && !CONFIG_USER_ONLY */ static void nios2_cpu_reset(DeviceState *dev) { @@ -223,6 +225,7 @@ static const struct TCGCPUOps nios2_tcg_ops = { .tlb_fill = nios2_cpu_tlb_fill, #ifndef CONFIG_USER_ONLY + .has_work = nios2_cpu_has_work, .cpu_exec_interrupt = nios2_cpu_exec_interrupt, .do_interrupt = nios2_cpu_do_interrupt, .do_unaligned_access = nios2_cpu_do_unaligned_access, @@ -241,7 +244,6 @@ static void nios2_cpu_class_init(ObjectClass *oc, void *data) device_class_set_parent_reset(dc, nios2_cpu_reset, &ncc->parent_reset); cc->class_by_name = nios2_cpu_class_by_name; - cc->has_work = nios2_cpu_has_work; cc->dump_state = nios2_cpu_dump_state; cc->set_pc = nios2_cpu_set_pc; cc->disas_set_info = nios2_cpu_disas_set_info;