From patchwork Wed Nov 3 18:40:20 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Marek_Marczykowski-G=C3=B3recki?= X-Patchwork-Id: 12601463 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3DCBBC433F5 for ; Wed, 3 Nov 2021 18:41:08 +0000 (UTC) Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id E2AA96109F for ; Wed, 3 Nov 2021 18:41:07 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org E2AA96109F Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=invisiblethingslab.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=lists.xenproject.org Received: from list by lists.xenproject.org with outflank-mailman.221118.382660 (Exim 4.92) (envelope-from ) id 1miLBi-0007lY-9t; Wed, 03 Nov 2021 18:40:42 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 221118.382660; Wed, 03 Nov 2021 18:40:42 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1miLBi-0007lR-66; Wed, 03 Nov 2021 18:40:42 +0000 Received: by outflank-mailman (input) for mailman id 221118; Wed, 03 Nov 2021 18:40:41 +0000 Received: from se1-gles-flk1-in.inumbo.com ([94.247.172.50] helo=se1-gles-flk1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1miLBh-0007lL-72 for xen-devel@lists.xenproject.org; Wed, 03 Nov 2021 18:40:41 +0000 Received: from out4-smtp.messagingengine.com (out4-smtp.messagingengine.com [66.111.4.28]) by se1-gles-flk1.inumbo.com (Halon) with ESMTPS id 89dbeffd-3cd5-11ec-a9d2-d9f7a1cc8784; Wed, 03 Nov 2021 19:40:39 +0100 (CET) Received: from compute4.internal (compute4.nyi.internal [10.202.2.44]) by mailout.nyi.internal (Postfix) with ESMTP id B55FC5C0191; Wed, 3 Nov 2021 14:40:37 -0400 (EDT) Received: from mailfrontend2 ([10.202.2.163]) by compute4.internal (MEProxy); Wed, 03 Nov 2021 14:40:37 -0400 Received: by mail.messagingengine.com (Postfix) with ESMTPA; Wed, 3 Nov 2021 14:40:36 -0400 (EDT) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 89dbeffd-3cd5-11ec-a9d2-d9f7a1cc8784 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:content-transfer-encoding:content-type :date:from:message-id:mime-version:subject:to:x-me-proxy :x-me-proxy:x-me-sender:x-me-sender:x-sasl-enc; s=fm1; bh=gVU9tB 42BsY+gMOp4NsCDMzjhsyHYtjFguFfI9f80Wg=; b=ml5mUmEAHe7+lWKSmf89GZ 2Ys0ZfPZHkmKjQ1LLMmBPKu7C2Eyz+p6M6XwjNez2/NClaZgdmYavPLRNQyJCNP1 3zjStRnHK7Sd1vRf9RwnTonlT7DK36z8O2zFFRwtK0fL5aT0XuFPANiwybQa44A/ CEq0R7CoX8y2ZJY992EtaSipVE6aVnA3XpUWCLyL+FIL2iKuT7NH4Fk/sruSWU4a /EqHpNTCJg5Sweh36UAG7sOUXszbp/VrsBDSU20hRy353QXgyEFf7UMoY36v4Te9 0jXTWBsYPuuMmYdWD67Rb7MRH9se+pZZWPL/DcFSljdXQbw2srwsIcC1dGlq/pog == X-ME-Sender: X-ME-Received: X-ME-Proxy-Cause: gggruggvucftvghtrhhoucdtuddrgedvuddrtddvgdduuddvucetufdoteggodetrfdotf fvucfrrhhofhhilhgvmecuhfgrshhtofgrihhlpdfqfgfvpdfurfetoffkrfgpnffqhgen uceurghilhhouhhtmecufedttdenucesvcftvggtihhpihgvnhhtshculddquddttddmne cujfgurhephffvufffkffogggtohfgsehtkeertdertdejnecuhfhrohhmpeforghrvghk ucforghrtgiihihkohifshhkihdqifpkrhgvtghkihcuoehmrghrmhgrrhgvkhesihhnvh hishhisghlvghthhhinhhgshhlrggsrdgtohhmqeenucggtffrrghtthgvrhhnpeetgeet keeukeffhfejueeludehtedtkeeuiedtgffgtdfhveefueeiiefhudehgeenucevlhhush htvghrufhiiigvpedtnecurfgrrhgrmhepmhgrihhlfhhrohhmpehmrghrmhgrrhgvkhes ihhnvhhishhisghlvghthhhinhhgshhlrggsrdgtohhm X-ME-Proxy: From: =?utf-8?q?Marek_Marczykowski-G=C3=B3recki?= To: xen-devel@lists.xenproject.org Cc: =?utf-8?q?Marek_Marczykowski-G=C3=B3recki?= , Jan Beulich , Ian Jackson , Andrew Cooper , =?utf-8?q?Roger_Pau_Monn=C3=A9?= , Wei Liu Subject: [PATCH-4.16 v2] x86/xstate: reset cached register values on resume Date: Wed, 3 Nov 2021 19:40:20 +0100 Message-Id: <20211103184020.1276465-1-marmarek@invisiblethingslab.com> X-Mailer: git-send-email 2.31.1 MIME-Version: 1.0 Organization: Invisible Things Lab set_xcr0() and set_msr_xss() use cached value to avoid setting the register to the same value over and over. But suspend/resume implicitly reset the registers and since percpu areas are not deallocated on suspend anymore, the cache gets stale. Reset the cache on resume, to ensure the next write will really hit the hardware. Choose value 0, as it will never be a legitimate write to those registers - and so, will force write (and cache update). Note the cache is used io get_xcr0() and get_msr_xss() too, but: - set_xcr0() is called few lines below in xstate_init(), so it will update the cache with appropriate value - get_msr_xss() is not used anywhere - and thus not before any set_msr_xss() that will fill the cache Fixes: aca2a985a55a "xen: don't free percpu areas during suspend" Signed-off-by: Marek Marczykowski-Górecki Reviewed-by: Jan Beulich --- Changes in v2: - adjust xss init value per Jan request For 4.16: this unbreaks S3 resume, it was posted initially back in August and is shipped in Qubes since September (although backported to 4.14, not unstable) with no reported regressions. Cc: Ian Jackson --- xen/arch/x86/xstate.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/xen/arch/x86/xstate.c b/xen/arch/x86/xstate.c index 6aaf9a2f1546..a16dfbb3877b 100644 --- a/xen/arch/x86/xstate.c +++ b/xen/arch/x86/xstate.c @@ -642,6 +642,13 @@ void xstate_init(struct cpuinfo_x86 *c) return; } + /* + * Clear the cached value to make set_xcr0() and set_msr_xss() really + * write it. + */ + this_cpu(xcr0) = 0; + this_cpu(xss) = ~0; + cpuid_count(XSTATE_CPUID, 0, &eax, &ebx, &ecx, &edx); feature_mask = (((u64)edx << 32) | eax) & XCNTXT_MASK; BUG_ON(!valid_xcr0(feature_mask));