@@ -153,15 +153,6 @@ ifneq ($(words $(subst :, ,$(abs_srctree))), 1)
$(error source directory cannot contain spaces or colons)
endif
-ifneq ($(abs_srctree),$(abs_objtree))
-# Look for make include files relative to root of kernel src
-#
-# This does not become effective immediately because MAKEFLAGS is re-parsed
-# once after the Makefile is read. We need to invoke sub-make.
-MAKEFLAGS += --include-dir=$(abs_srctree)
-need-sub-make := 1
-endif
-
export abs_srctree abs_objtree
export root-make-done := y
@@ -225,7 +216,7 @@ ifneq ($(filter %config,$(MAKECMDGOALS)),)
config-build := y
endif
-include scripts/Kbuild.include
+include $(srctree)/scripts/Kbuild.include
ARCH=$(XEN_TARGET_ARCH)
SRCARCH=$(shell echo $(ARCH) | \
@@ -104,7 +104,7 @@ noubsan-y := $(addprefix $(obj)/,$(noubsan-y))
# $(sort ...) is used here to remove duplicated words and excessive spaces.
hostprogs-y := $(sort $(hostprogs-y))
ifneq ($(hostprogs-y),)
-include scripts/Makefile.host
+include $(srctree)/scripts/Makefile.host
endif
# subdir-builtin may contain duplications. Use $(sort ...)
@@ -1,4 +1,4 @@
-include $(src)/Makefile.libfdt
+include $(srcdir)/Makefile.libfdt
SECTIONS := text data $(SPECIAL_DATA_SECTIONS)
OBJCOPYFLAGS := $(foreach s,$(SECTIONS),--rename-section .$(s)=.init.$(s))
@@ -12,7 +12,7 @@ clean::
include $(srctree)/scripts/Kbuild.include
-include $(src)/Makefile
+include $(srcdir)/Makefile
# Figure out what we need to clean from the various variables
# ==========================================================================