diff mbox series

[4/3] x86/vPMU: Drop supported parameter from the wrmsr path

Message ID 20211130220111.23815-1-andrew.cooper3@citrix.com (mailing list archive)
State New, archived
Headers show
Series x86/vPMU: adjustements to vendor hooks treatment | expand

Commit Message

Andrew Cooper Nov. 30, 2021, 10:01 p.m. UTC 
The supported parameter was added in 2d9b91f1aeaa ("VMX/vPMU: fix DebugCtl MSR
handling"), it laid the groundwork for XSA-269, and in the meantime
2a8a8e99feb9 ("x86/vtx: Fix the checking for unknown/invalid MSR_DEBUGCTL
bits") totally rewrote MSR_DEBUGCTL handling.

Strip out the parameter again.

Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com>
---
CC: Jan Beulich <JBeulich@suse.com>
CC: Roger Pau Monné <roger.pau@citrix.com>
CC: Wei Liu <wl@xen.org>
---
 xen/arch/x86/cpu/vpmu.c        |  5 ++---
 xen/arch/x86/cpu/vpmu_amd.c    |  5 +----
 xen/arch/x86/cpu/vpmu_intel.c  |  5 +----
 xen/arch/x86/hvm/svm/svm.c     |  2 +-
 xen/arch/x86/hvm/vmx/vmx.c     |  2 +-
 xen/arch/x86/pv/emul-priv-op.c |  2 +-
 xen/include/asm-x86/vpmu.h     | 13 +++++--------
 7 files changed, 12 insertions(+), 22 deletions(-)

Comments

Jan Beulich Dec. 1, 2021, 7:49 a.m. UTC | #1 
On 30.11.2021 23:01, Andrew Cooper wrote:
> The supported parameter was added in 2d9b91f1aeaa ("VMX/vPMU: fix DebugCtl MSR
> handling"), it laid the groundwork for XSA-269, and in the meantime
> 2a8a8e99feb9 ("x86/vtx: Fix the checking for unknown/invalid MSR_DEBUGCTL
> bits") totally rewrote MSR_DEBUGCTL handling.
> 
> Strip out the parameter again.
> 
> Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com>

Reviewed-by: Jan Beulich <jbeulich@suse.com>
albeit please with ...

> @@ -113,14 +111,13 @@ void vpmu_save(struct vcpu *v);
>  int vpmu_load(struct vcpu *v, bool_t from_guest);
>  void vpmu_dump(struct vcpu *v);
>  
> -static inline int vpmu_do_wrmsr(unsigned int msr, uint64_t msr_content,
> -                                uint64_t supported)
> +static inline int vpmu_do_wrmsr(unsigned int msr, uint64_t msr_content)
>  {
> -    return vpmu_do_msr(msr, &msr_content, supported, 1);
> +    return vpmu_do_msr(msr, &msr_content, 1);

... "true" and ...

>  }
>  static inline int vpmu_do_rdmsr(unsigned int msr, uint64_t *msr_content)
>  {
> -    return vpmu_do_msr(msr, msr_content, 0, 0);
> +    return vpmu_do_msr(msr, msr_content, 0);

... "false" used respectively, as you're touching this anyway.

Jan
diff mbox series

Patch

diff --git a/xen/arch/x86/cpu/vpmu.c b/xen/arch/x86/cpu/vpmu.c
index 7fd69a2a58e3..8ec4547bedf4 100644
--- a/xen/arch/x86/cpu/vpmu.c
+++ b/xen/arch/x86/cpu/vpmu.c
@@ -116,8 +116,7 @@  void vpmu_lvtpc_update(uint32_t val)
         apic_write(APIC_LVTPC, vpmu->hw_lapic_lvtpc);
 }
 
-int vpmu_do_msr(unsigned int msr, uint64_t *msr_content,
-                uint64_t supported, bool_t is_write)
+int vpmu_do_msr(unsigned int msr, uint64_t *msr_content, bool is_write)
 {
     struct vcpu *curr = current;
     struct vpmu_struct *vpmu;
@@ -137,7 +136,7 @@  int vpmu_do_msr(unsigned int msr, uint64_t *msr_content,
         goto nop;
 
     if ( is_write )
-        ret = alternative_call(vpmu_ops.do_wrmsr, msr, *msr_content, supported);
+        ret = alternative_call(vpmu_ops.do_wrmsr, msr, *msr_content);
     else
         ret = alternative_call(vpmu_ops.do_rdmsr, msr, msr_content);
 
diff --git a/xen/arch/x86/cpu/vpmu_amd.c b/xen/arch/x86/cpu/vpmu_amd.c
index b28c78b81109..903fe1887ef0 100644
--- a/xen/arch/x86/cpu/vpmu_amd.c
+++ b/xen/arch/x86/cpu/vpmu_amd.c
@@ -348,16 +348,13 @@  static void context_update(unsigned int msr, u64 msr_content)
     }
 }
 
-static int amd_vpmu_do_wrmsr(unsigned int msr, uint64_t msr_content,
-                             uint64_t supported)
+static int amd_vpmu_do_wrmsr(unsigned int msr, uint64_t msr_content)
 {
     struct vcpu *v = current;
     struct vpmu_struct *vpmu = vcpu_vpmu(v);
     unsigned int idx = 0;
     int type = get_pmu_reg_type(msr, &idx);
 
-    ASSERT(!supported);
-
     if ( (type == MSR_TYPE_CTRL ) &&
          ((msr_content & CTRL_RSVD_MASK) != ctrl_rsvd[idx]) )
         return -EINVAL;
diff --git a/xen/arch/x86/cpu/vpmu_intel.c b/xen/arch/x86/cpu/vpmu_intel.c
index 63e798b9edac..076882c615f4 100644
--- a/xen/arch/x86/cpu/vpmu_intel.c
+++ b/xen/arch/x86/cpu/vpmu_intel.c
@@ -522,8 +522,7 @@  static int core2_vpmu_msr_common_check(u32 msr_index, int *type, int *index)
     return 1;
 }
 
-static int core2_vpmu_do_wrmsr(unsigned int msr, uint64_t msr_content,
-                               uint64_t supported)
+static int core2_vpmu_do_wrmsr(unsigned int msr, uint64_t msr_content)
 {
     int i, tmp;
     int type = -1, index = -1;
@@ -535,8 +534,6 @@  static int core2_vpmu_do_wrmsr(unsigned int msr, uint64_t msr_content,
     if ( !core2_vpmu_msr_common_check(msr, &type, &index) )
         return -EINVAL;
 
-    ASSERT(!supported);
-
     if ( (type == MSR_TYPE_COUNTER) && (msr_content & fixed_counters_mask) )
         /* Writing unsupported bits to a fixed counter */
         return -EINVAL;
diff --git a/xen/arch/x86/hvm/svm/svm.c b/xen/arch/x86/hvm/svm/svm.c
index f0e10dec046e..fae39c4b4cbd 100644
--- a/xen/arch/x86/hvm/svm/svm.c
+++ b/xen/arch/x86/hvm/svm/svm.c
@@ -2113,7 +2113,7 @@  static int svm_msr_write_intercept(unsigned int msr, uint64_t msr_content)
     case MSR_AMD_FAM15H_EVNTSEL3:
     case MSR_AMD_FAM15H_EVNTSEL4:
     case MSR_AMD_FAM15H_EVNTSEL5:
-        if ( vpmu_do_wrmsr(msr, msr_content, 0) )
+        if ( vpmu_do_wrmsr(msr, msr_content) )
             goto gpf;
         break;
 
diff --git a/xen/arch/x86/hvm/vmx/vmx.c b/xen/arch/x86/hvm/vmx/vmx.c
index 37c31c08b984..a7a0d662342a 100644
--- a/xen/arch/x86/hvm/vmx/vmx.c
+++ b/xen/arch/x86/hvm/vmx/vmx.c
@@ -3487,7 +3487,7 @@  static int vmx_msr_write_intercept(unsigned int msr, uint64_t msr_content)
     case MSR_CORE_PERF_FIXED_CTR_CTRL...MSR_CORE_PERF_GLOBAL_OVF_CTRL:
     case MSR_IA32_PEBS_ENABLE:
     case MSR_IA32_DS_AREA:
-         if ( vpmu_do_wrmsr(msr, msr_content, 0) )
+         if ( vpmu_do_wrmsr(msr, msr_content) )
             goto gp_fault;
         break;
 
diff --git a/xen/arch/x86/pv/emul-priv-op.c b/xen/arch/x86/pv/emul-priv-op.c
index 7f4279a0517b..8ba65178e98f 100644
--- a/xen/arch/x86/pv/emul-priv-op.c
+++ b/xen/arch/x86/pv/emul-priv-op.c
@@ -1163,7 +1163,7 @@  static int write_msr(unsigned int reg, uint64_t val,
                      !is_hardware_domain(currd) )
                     return X86EMUL_OKAY;
 
-                if ( vpmu_do_wrmsr(reg, val, 0) )
+                if ( vpmu_do_wrmsr(reg, val) )
                     break;
                 return X86EMUL_OKAY;
             }
diff --git a/xen/include/asm-x86/vpmu.h b/xen/include/asm-x86/vpmu.h
index ccf5a0cf90b9..80656891e5a3 100644
--- a/xen/include/asm-x86/vpmu.h
+++ b/xen/include/asm-x86/vpmu.h
@@ -40,8 +40,7 @@ 
 /* Arch specific operations shared by all vpmus */
 struct arch_vpmu_ops {
     int (*initialise)(struct vcpu *v);
-    int (*do_wrmsr)(unsigned int msr, uint64_t msr_content,
-                    uint64_t supported);
+    int (*do_wrmsr)(unsigned int msr, uint64_t msr_content);
     int (*do_rdmsr)(unsigned int msr, uint64_t *msr_content);
     int (*do_interrupt)(struct cpu_user_regs *regs);
     void (*arch_vpmu_destroy)(struct vcpu *v);
@@ -104,8 +103,7 @@  static inline bool_t vpmu_are_all_set(const struct vpmu_struct *vpmu,
 }
 
 void vpmu_lvtpc_update(uint32_t val);
-int vpmu_do_msr(unsigned int msr, uint64_t *msr_content,
-                uint64_t supported, bool_t is_write);
+int vpmu_do_msr(unsigned int msr, uint64_t *msr_content, bool is_write);
 void vpmu_do_interrupt(struct cpu_user_regs *regs);
 void vpmu_initialise(struct vcpu *v);
 void vpmu_destroy(struct vcpu *v);
@@ -113,14 +111,13 @@  void vpmu_save(struct vcpu *v);
 int vpmu_load(struct vcpu *v, bool_t from_guest);
 void vpmu_dump(struct vcpu *v);
 
-static inline int vpmu_do_wrmsr(unsigned int msr, uint64_t msr_content,
-                                uint64_t supported)
+static inline int vpmu_do_wrmsr(unsigned int msr, uint64_t msr_content)
 {
-    return vpmu_do_msr(msr, &msr_content, supported, 1);
+    return vpmu_do_msr(msr, &msr_content, 1);
 }
 static inline int vpmu_do_rdmsr(unsigned int msr, uint64_t *msr_content)
 {
-    return vpmu_do_msr(msr, msr_content, 0, 0);
+    return vpmu_do_msr(msr, msr_content, 0);
 }
 
 extern unsigned int vpmu_mode;