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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?utf-8?q?vOo+4lG2BX3ExjMNVLRQw58sjCxz?= =?utf-8?q?/hpF6cHbqlbFkQvjo6ubjD5TgVMjejaoD5qKAcCuduVthdvyyer/asM3ZUE+WaJh8?= =?utf-8?q?t748CVDZYFk+x17W7VqPQ6GjBdcaKU4LA0D2KhioS1G4RlFHnDQUOf2vHs4Y+mhPj?= =?utf-8?q?fJQNFu15+r+C1kd2aHPcOLrX9WmrNgDJYTsndLH/oCuajOjlhozRO9lA3MesQCP8G?= =?utf-8?q?t1n0A3HvY5zs5HH5hXdxYV08dFZVEq/4KAtG1A15sUFFwAMHdeeyRCmZMWE1yU9uH?= =?utf-8?q?jTtknIfXBscVYUzOuUooDVuI9OxzUlbEDFHa3AEcxaF+urLfOZE4C5S4iIn81VxlV?= =?utf-8?q?qRm4HYMEQjLOS6wxo8g/xaf6A2bP49Wk7tecgSgEfQbwW9g2nMKEYtIGo6u1kd0dd?= =?utf-8?q?EPrQzgjhsB/F93l6m9OYRdkS4su0+iSxKPS0ly5UdJmqe/hR/q+bocU/3/yW38h0z?= =?utf-8?q?1yk6D3F49Dd+tvaalZK0+v4Zao4WYo7OKpPcb4jShp6kWvj5V2sCbFmLe6xInZsAl?= =?utf-8?q?KWd57UWx0KvAtxaKJT7idCvX8BVXPwwYK3rG+yDU1UW5bWFJFUowO80hPtW1E9r2d?= =?utf-8?q?ZdYXCanJrY+SL86rqUSQntu3Gx8ejLd5hmG7DIi5RP8oj/LbaEaO+deXcN5R0ZfqS?= =?utf-8?q?TEm8KgCfIr0a/NcBHw5kDDIvgaptVzPWg9bWy1Q07/jp7ZBm9bnbyOy7yhEsVC+yP?= =?utf-8?q?oI3845/0CIjTAxEXBnPt9LzoOitBHsdMKNZ+UZnkHzzsyB8ZZvliAZbi2UWb0kLEY?= =?utf-8?q?JgEA66D/oHfJfDaNugVJ7VyHgmLzsD34MyTxC+D5Wvd9oNiawcokdK/IlKG5H8epn?= =?utf-8?q?5nkdrc1Tq4TRRutCoRgBvFqj9xbXn+vzrB+hwAlreJ/h5l7tvPEFpjPutwI4wPUdl?= =?utf-8?q?ziVCKPy2PLYqla3+uJnSNEGetikUk2SX8OXiStyTJYayq7l+DiKtiAV+/KDp55d6g?= =?utf-8?q?UR82P7cAoAzcn/GpcO/p7nOB5RSyfAvl9QRPhlzjqKpXFtyW3b9Sk4aGdspZTcL0K?= =?utf-8?q?NQPuWtzru+mkgyuFDm9PK6qZ8rAJnYsjekXbkmykJItxP4/Zqht6RUxXIDG6Oacg6?= =?utf-8?q?W56ph8NUPhV8GDVSYMIHrhnzH6gugwNQ6wpwTMcd8WJWa1zQCi4NUdMQ3qwQW5v9n?= =?utf-8?q?5X4cAobteTkdIjBwGHWMovmUjrvgQlYaIUPXbJqbHoLv5WF3I/mR01nhUAlHa0OlP?= =?utf-8?q?iUEt3asrcuOvwAOaX5LufeBeHI2ZY3OGuAWGpWUHhS150WxNQe/oPix0RzI9OpSE3?= =?utf-8?q?ZznVaSBWFIJzr67J7XV9fUh6DnHkWEN5Ff6VQApIgNe/g+LlLWyh2R8ig/d5xZc8H?= =?utf-8?q?DvL9VymaxNoLLeqrqUXWXraO2oXtqqRJ6XSGmvJ1FzF5TzMPIy3FJxjv7iGGi7BFe?= =?utf-8?q?Se4jQCC/rRVVy1kqYZRNxHOeLAyq6F4NUMM1acqhcSb35j5+6GNN8EzHkPQpDCaJL?= =?utf-8?q?DOylLOGWNwiGBDLOUl8PYS/2s5pc+n8E2gfNI39IBJ/fwb8F3nhOo1atw+DvwCnJB?= =?utf-8?q?MW8pjTtgV4CC38J1fDJdd+bE+X3/vh7/uRvcOra/V2ijaG05XNRkbm0=3D?= X-MS-Exchange-CrossTenant-Network-Message-Id: 4f9f5769-2bdc-4f64-f8f7-08d9e5a283e9 X-MS-Exchange-CrossTenant-AuthSource: DS7PR03MB5608.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 01 Feb 2022 16:47:21.1184 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 335836de-42ef-43a2-b145-348c2ee9ca5b X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: RLrJImdvFwdp/DERnpT8YRumsTXvj5u7Psmue6uFIHclhnyw/6tdtLfC8YHitURTuVhkuwd4y868rcN0QFdFRw== X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN6PR03MB3565 X-OriginatorOrg: citrix.com Use the logic to set shadow SPEC_CTRL values in order to implement support for VIRT_SPEC_CTRL (signaled by VIRT_SSBD CPUID flag) for HVM guests. This includes using the spec_ctrl vCPU MSR variable to store the guest set value of VIRT_SPEC_CTRL.SSBD. Note that VIRT_SSBD is only set in the HVM max CPUID policy, as the default should be to expose SPEC_CTRL only and support VIRT_SPEC_CTRL for migration compatibility. Suggested-by: Andrew Cooper Signed-off-by: Roger Pau Monné --- docs/misc/xen-command-line.pandoc | 5 +++-- xen/arch/x86/cpuid.c | 7 +++++++ xen/arch/x86/hvm/hvm.c | 1 + xen/arch/x86/include/asm/msr.h | 6 +++++- xen/arch/x86/msr.c | 15 +++++++++++++++ xen/arch/x86/spec_ctrl.c | 3 ++- xen/include/public/arch-x86/cpufeatureset.h | 2 +- 7 files changed, 34 insertions(+), 5 deletions(-) diff --git a/docs/misc/xen-command-line.pandoc b/docs/misc/xen-command-line.pandoc index 6b3da6ddc1..081e10f80b 100644 --- a/docs/misc/xen-command-line.pandoc +++ b/docs/misc/xen-command-line.pandoc @@ -2273,8 +2273,9 @@ to use. * `pv=` and `hvm=` offer control over all suboptions for PV and HVM guests respectively. * `msr-sc=` offers control over Xen's support for manipulating `MSR_SPEC_CTRL` - on entry and exit. These blocks are necessary to virtualise support for - guests and if disabled, guests will be unable to use IBRS/STIBP/SSBD/etc. + and/or `MSR_VIRT_SPEC_CTRL` on entry and exit. These blocks are necessary to + virtualise support for guests and if disabled, guests will be unable to use + IBRS/STIBP/SSBD/etc. * `rsb=` offers control over whether to overwrite the Return Stack Buffer / Return Address Stack on entry to Xen. * `md-clear=` offers control over whether to use VERW to flush diff --git a/xen/arch/x86/cpuid.c b/xen/arch/x86/cpuid.c index e24dd283e7..29b4cfc9e6 100644 --- a/xen/arch/x86/cpuid.c +++ b/xen/arch/x86/cpuid.c @@ -543,6 +543,13 @@ static void __init calculate_hvm_max_policy(void) __clear_bit(X86_FEATURE_IBRSB, hvm_featureset); __clear_bit(X86_FEATURE_IBRS, hvm_featureset); } + else + /* + * If SPEC_CTRL is available VIRT_SPEC_CTRL can also be implemented as + * it's a subset of the controls exposed in SPEC_CTRL (SSBD only). + * Expose in the max policy for compatibility migration. + */ + __set_bit(X86_FEATURE_VIRT_SSBD, hvm_featureset); /* * With VT-x, some features are only supported by Xen if dedicated diff --git a/xen/arch/x86/hvm/hvm.c b/xen/arch/x86/hvm/hvm.c index c4ddb8607d..3400c9299c 100644 --- a/xen/arch/x86/hvm/hvm.c +++ b/xen/arch/x86/hvm/hvm.c @@ -1332,6 +1332,7 @@ static const uint32_t msrs_to_send[] = { MSR_INTEL_MISC_FEATURES_ENABLES, MSR_IA32_BNDCFGS, MSR_IA32_XSS, + MSR_VIRT_SPEC_CTRL, MSR_AMD64_DR0_ADDRESS_MASK, MSR_AMD64_DR1_ADDRESS_MASK, MSR_AMD64_DR2_ADDRESS_MASK, diff --git a/xen/arch/x86/include/asm/msr.h b/xen/arch/x86/include/asm/msr.h index ce4fe51afe..98f6b79e09 100644 --- a/xen/arch/x86/include/asm/msr.h +++ b/xen/arch/x86/include/asm/msr.h @@ -291,6 +291,7 @@ struct vcpu_msrs { /* * 0x00000048 - MSR_SPEC_CTRL + * 0xc001011f - MSR_VIRT_SPEC_CTRL * * For PV guests, this holds the guest kernel value. It is accessed on * every entry/exit path. @@ -301,7 +302,10 @@ struct vcpu_msrs * For SVM, the guest value lives in the VMCB, and hardware saves/restores * the host value automatically. However, guests run with the OR of the * host and guest value, which allows Xen to set protections behind the - * guest's back. + * guest's back. Use such functionality in order to implement support for + * VIRT_SPEC_CTRL as a shadow value of SPEC_CTRL and thus store the value + * of VIRT_SPEC_CTRL in this field, taking advantage of both MSRs having + * compatible layouts. * * We must clear/restore Xen's value before/after VMRUN to avoid unduly * influencing the guest. In order to support "behind the guest's back" diff --git a/xen/arch/x86/msr.c b/xen/arch/x86/msr.c index 4ac5b5a048..aa74cfde6c 100644 --- a/xen/arch/x86/msr.c +++ b/xen/arch/x86/msr.c @@ -381,6 +381,13 @@ int guest_rdmsr(struct vcpu *v, uint32_t msr, uint64_t *val) ? K8_HWCR_TSC_FREQ_SEL : 0; break; + case MSR_VIRT_SPEC_CTRL: + if ( !cp->extd.virt_ssbd ) + goto gp_fault; + + *val = msrs->spec_ctrl.raw & SPEC_CTRL_SSBD; + break; + case MSR_AMD64_DE_CFG: if ( !(cp->x86_vendor & (X86_VENDOR_AMD | X86_VENDOR_HYGON)) ) goto gp_fault; @@ -666,6 +673,14 @@ int guest_wrmsr(struct vcpu *v, uint32_t msr, uint64_t val) wrmsr_tsc_aux(val); break; + case MSR_VIRT_SPEC_CTRL: + if ( !cp->extd.virt_ssbd ) + goto gp_fault; + + /* Only supports SSBD bit, the rest are ignored. */ + msrs->spec_ctrl.raw = val & SPEC_CTRL_SSBD; + break; + case MSR_AMD64_DE_CFG: /* * OpenBSD 6.7 will panic if writing to DE_CFG triggers a #GP: diff --git a/xen/arch/x86/spec_ctrl.c b/xen/arch/x86/spec_ctrl.c index ee862089b7..64b154b2d3 100644 --- a/xen/arch/x86/spec_ctrl.c +++ b/xen/arch/x86/spec_ctrl.c @@ -395,12 +395,13 @@ static void __init print_details(enum ind_thunk thunk, uint64_t caps) * mitigation support for guests. */ #ifdef CONFIG_HVM - printk(" Support for HVM VMs:%s%s%s%s%s\n", + printk(" Support for HVM VMs:%s%s%s%s%s%s\n", (boot_cpu_has(X86_FEATURE_SC_MSR_HVM) || boot_cpu_has(X86_FEATURE_SC_RSB_HVM) || boot_cpu_has(X86_FEATURE_MD_CLEAR) || opt_eager_fpu) ? "" : " None", boot_cpu_has(X86_FEATURE_SC_MSR_HVM) ? " MSR_SPEC_CTRL" : "", + boot_cpu_has(X86_FEATURE_SC_MSR_HVM) ? " MSR_VIRT_SPEC_CTRL" : "", boot_cpu_has(X86_FEATURE_SC_RSB_HVM) ? " RSB" : "", opt_eager_fpu ? " EAGER_FPU" : "", boot_cpu_has(X86_FEATURE_MD_CLEAR) ? " MD_CLEAR" : ""); diff --git a/xen/include/public/arch-x86/cpufeatureset.h b/xen/include/public/arch-x86/cpufeatureset.h index 957df23b65..b9ab878ec1 100644 --- a/xen/include/public/arch-x86/cpufeatureset.h +++ b/xen/include/public/arch-x86/cpufeatureset.h @@ -265,7 +265,7 @@ XEN_CPUFEATURE(IBRS_SAME_MODE, 8*32+19) /*S IBRS provides same-mode protection XEN_CPUFEATURE(NO_LMSL, 8*32+20) /*S EFER.LMSLE no longer supported. */ XEN_CPUFEATURE(AMD_PPIN, 8*32+23) /* Protected Processor Inventory Number */ XEN_CPUFEATURE(AMD_SSBD, 8*32+24) /*S MSR_SPEC_CTRL.SSBD available */ -XEN_CPUFEATURE(VIRT_SSBD, 8*32+25) /* MSR_VIRT_SPEC_CTRL.SSBD */ +XEN_CPUFEATURE(VIRT_SSBD, 8*32+25) /*!s MSR_VIRT_SPEC_CTRL.SSBD */ XEN_CPUFEATURE(SSB_NO, 8*32+26) /*A Hardware not vulnerable to SSB */ XEN_CPUFEATURE(PSFD, 8*32+28) /*S MSR_SPEC_CTRL.PSFD */