@@ -234,6 +234,8 @@ int libxl_cpuid_parse_config(libxl_cpuid_policy_list *cpuid, const char* str)
{"fsrs", 0x00000007, 1, CPUID_REG_EAX, 11, 1},
{"fsrcs", 0x00000007, 1, CPUID_REG_EAX, 12, 1},
+ {"intel-psfd", 0x00000007, 2, CPUID_REG_EDX, 0, 1},
+
{"lahfsahf", 0x80000001, NA, CPUID_REG_ECX, 0, 1},
{"cmplegacy", 0x80000001, NA, CPUID_REG_ECX, 1, 1},
{"svm", 0x80000001, NA, CPUID_REG_ECX, 2, 1},
@@ -202,6 +202,7 @@ static const char *const str_7b1[32] =
static const char *const str_7d2[32] =
{
+ [ 0] = "intel-psfd",
};
static const struct {
@@ -443,7 +443,7 @@ int guest_rdmsr(struct vcpu *v, uint32_t msr, uint64_t *val)
uint64_t msr_spec_ctrl_valid_bits(const struct cpuid_policy *cp)
{
bool ssbd = cp->feat.ssbd || cp->extd.amd_ssbd;
- bool psfd = cp->extd.psfd;
+ bool psfd = cp->feat.intel_psfd || cp->extd.psfd;
/*
* Note: SPEC_CTRL_STIBP is specified as safe to use (i.e. ignored)
@@ -307,11 +307,13 @@ custom_param("pv-l1tf", parse_pv_l1tf);
static void __init print_details(enum ind_thunk thunk, uint64_t caps)
{
- unsigned int _7d0 = 0, e8b = 0, tmp;
+ unsigned int _7d0 = 0, _7d2 = 0, e8b = 0, max = 0, tmp;
/* Collect diagnostics about available mitigations. */
if ( boot_cpu_data.cpuid_level >= 7 )
- cpuid_count(7, 0, &tmp, &tmp, &tmp, &_7d0);
+ cpuid_count(7, 0, &max, &tmp, &tmp, &_7d0);
+ if ( max >= 2 )
+ cpuid_count(7, 2, &tmp, &tmp, &tmp, &_7d2);
if ( boot_cpu_data.extended_cpuid_level >= 0x80000008 )
cpuid(0x80000008, &tmp, &e8b, &tmp, &tmp);
@@ -345,6 +347,7 @@ static void __init print_details(enum ind_thunk thunk, uint64_t caps)
(_7d0 & cpufeat_mask(X86_FEATURE_STIBP)) ? " STIBP" : "",
(e8b & cpufeat_mask(X86_FEATURE_AMD_SSBD)) ||
(_7d0 & cpufeat_mask(X86_FEATURE_SSBD)) ? " SSBD" : "",
+ (_7d2 & cpufeat_mask(X86_FEATURE_INTEL_PSFD)) ||
(e8b & cpufeat_mask(X86_FEATURE_PSFD)) ? " PSFD" : "",
(_7d0 & cpufeat_mask(X86_FEATURE_L1D_FLUSH)) ? " L1D_FLUSH" : "",
(_7d0 & cpufeat_mask(X86_FEATURE_MD_CLEAR)) ? " MD_CLEAR" : "",
@@ -303,6 +303,7 @@ XEN_CPUFEATURE(NSCB, 11*32+ 6) /*A Null Selector Clears Base (and
XEN_CPUFEATURE(INTEL_PPIN, 12*32+ 0) /* Protected Processor Inventory Number */
/* Intel-defined CPU features, CPUID level 0x00000007:2.edx, word 13 */
+XEN_CPUFEATURE(INTEL_PSFD, 13*32+ 0) /*A MSR_SPEC_CTRL.PSFD */
#endif /* XEN_CPUFEATURE */
@@ -287,7 +287,7 @@ def crunch_numbers(state):
# IBRSB/IBRS, and we pass this MSR directly to guests. Treating them
# as dependent features simplifies Xen's logic, and prevents the guest
# from seeing implausible configurations.
- IBRSB: [STIBP, SSBD],
+ IBRSB: [STIBP, SSBD, INTEL_PSFD],
IBRS: [AMD_STIBP, AMD_SSBD, PSFD,
IBRS_ALWAYS, IBRS_FAST, IBRS_SAME_MODE],
AMD_STIBP: [STIBP_ALWAYS],