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d="scan'208";a="73179186" From: Andrew Cooper To: Xen-devel CC: Andrew Cooper , Jan Beulich , =?utf-8?q?Roger_Pau_Monn=C3=A9?= , Wei Liu Subject: [PATCH] x86/spec-ctrl: More MSR_ARCH_CAPS enumerations Date: Fri, 10 Jun 2022 17:00:50 +0100 Message-ID: <20220610160050.24221-1-andrew.cooper3@citrix.com> X-Mailer: git-send-email 2.11.0 MIME-Version: 1.0 https://www.intel.com/content/www/us/en/developer/articles/technical/software-security-guidance/best-practices/data-operand-independent-timing-isa-guidance.html https://www.intel.com/content/www/us/en/developer/articles/technical/software-security-guidance/advisory-guidance/running-average-power-limit-energy-reporting.html Signed-off-by: Andrew Cooper Reviewed-by: Jan Beulich --- CC: Jan Beulich CC: Roger Pau Monné CC: Wei Liu The SDM also lists #define ARCH_CAPS_OVERCLOCKING_STATUS (_AC(1, ULL) << 23) but I've got no idea what this is, nor the index of MSR_OVERCLOCKING_STATUS which is the thing allegedly enumerated by this. --- xen/arch/x86/include/asm/msr-index.h | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/xen/arch/x86/include/asm/msr-index.h b/xen/arch/x86/include/asm/msr-index.h index 6c250bfcadad..781584953654 100644 --- a/xen/arch/x86/include/asm/msr-index.h +++ b/xen/arch/x86/include/asm/msr-index.h @@ -51,6 +51,9 @@ #define PPIN_ENABLE (_AC(1, ULL) << 1) #define MSR_PPIN 0x0000004f +#define MSR_MISC_PACKAGE_CTRL 0x000000bc +#define PGK_CTRL_ENERGY_FILTER_EN (_AC(1, ULL) << 0) + #define MSR_CORE_CAPABILITIES 0x000000cf #define CORE_CAPS_SPLITLOCK_DETECT (_AC(1, ULL) << 5) @@ -71,6 +74,9 @@ #define ARCH_CAPS_IF_PSCHANGE_MC_NO (_AC(1, ULL) << 6) #define ARCH_CAPS_TSX_CTRL (_AC(1, ULL) << 7) #define ARCH_CAPS_TAA_NO (_AC(1, ULL) << 8) +#define ARCH_CAPS_MISC_PACKAGE_CTRL (_AC(1, ULL) << 10) +#define ARCH_CAPS_ENERGY_FILTERING (_AC(1, ULL) << 11) +#define ARCH_CAPS_DOITM (_AC(1, ULL) << 12) #define ARCH_CAPS_RRSBA (_AC(1, ULL) << 19) #define ARCH_CAPS_BHI_NO (_AC(1, ULL) << 20) @@ -149,6 +155,9 @@ #define PASID_PASID_MASK 0x000fffff #define PASID_VALID (_AC(1, ULL) << 31) +#define MSR_UARCH_MISC_CTRL 0x00001b01 +#define UARCH_CTRL_DOITM (_AC(1, ULL) << 0) + #define MSR_EFER 0xc0000080 /* Extended Feature Enable Register */ #define EFER_SCE (_AC(1, ULL) << 0) /* SYSCALL Enable */ #define EFER_LME (_AC(1, ULL) << 8) /* Long Mode Enable */