| Message ID | 20220718205009.3557-3-andrew.cooper3@citrix.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | XSA-407 followon fixes | expand |
On 18.07.2022 22:50, Andrew Cooper wrote: > The logic was written this way out of an abundance of caution, but the reality > is that AMD parts don't currently have the RAS-flushing side effect, and nor > do they intend to gain it. Nit: Looks like there's a stray (leftover from a re-write) "and" here? > This removes one WRMSR from the VMExit path by default on Zen2 systems. > > Fixes: 614cec7d79d7 ("x86/svm: VMEntry/Exit logic for MSR_SPEC_CTRL") > Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com> Reviewed-by: Jan Beulich <jbeulich@suse.com>
diff --git a/xen/arch/x86/hvm/svm/entry.S b/xen/arch/x86/hvm/svm/entry.S index 0ff4008060fa..a60d759f7108 100644 --- a/xen/arch/x86/hvm/svm/entry.S +++ b/xen/arch/x86/hvm/svm/entry.S @@ -113,15 +113,15 @@ __UNLIKELY_END(nsvm_hap) ALTERNATIVE "", DO_OVERWRITE_RSB, X86_FEATURE_SC_RSB_HVM .macro svm_vmexit_spec_ctrl - /* - * Write to MSR_SPEC_CTRL unconditionally, for the RAS[:32] - * flushing side effect. - */ - mov $MSR_SPEC_CTRL, %ecx movzbl CPUINFO_xen_spec_ctrl(%rsp), %eax + movzbl CPUINFO_last_spec_ctrl(%rsp), %edx + cmp %edx, %eax + je 1f /* Skip write if value is correct. */ + mov $MSR_SPEC_CTRL, %ecx xor %edx, %edx wrmsr mov %al, CPUINFO_last_spec_ctrl(%rsp) +1: .endm ALTERNATIVE "", svm_vmexit_spec_ctrl, X86_FEATURE_SC_MSR_HVM /* WARNING! `ret`, `call *`, `jmp *` not safe before this point. */
The logic was written this way out of an abundance of caution, but the reality is that AMD parts don't currently have the RAS-flushing side effect, and nor do they intend to gain it. This removes one WRMSR from the VMExit path by default on Zen2 systems. Fixes: 614cec7d79d7 ("x86/svm: VMEntry/Exit logic for MSR_SPEC_CTRL") Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com> --- CC: Jan Beulich <JBeulich@suse.com> CC: Roger Pau Monné <roger.pau@citrix.com> CC: Wei Liu <wl@xen.org> Zen3 doesn't get a speedup in general, because we use the WRMSR's to clear IBRS to avoid forcing it behind a VM's back. --- xen/arch/x86/hvm/svm/entry.S | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-)