| Message ID | 20221019143620.45814-1-ayankuma@amd.com (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | [XEN,v1] GICv3: Emulate GICD_IGRPMODR as RAZ / WI | expand |
Hi Ayan, On 19/10/2022 16:36, Ayan Kumar Halder wrote: > > > Refer GIC v3 specification (Arm IHI 0069H ID020922), IGRPMODR (similar to > IGROUPR) is relevant only when the guests run in secure/non-secure mode. > As Xen does not implement security extensions for guests, so the registers > are emulated as read as zero/write ignore. > > Signed-off-by: Ayan Kumar Halder <ayankuma@amd.com> > --- > > Observed the issue while running Zephyr on R52. > Also, found that KVM has similar behaviour. > > xen/arch/arm/include/asm/gic.h | 2 ++ > xen/arch/arm/vgic-v3.c | 4 ++++ > 2 files changed, 6 insertions(+) > > diff --git a/xen/arch/arm/include/asm/gic.h b/xen/arch/arm/include/asm/gic.h > index 76e3fa5dc4..998dd62651 100644 > --- a/xen/arch/arm/include/asm/gic.h > +++ b/xen/arch/arm/include/asm/gic.h > @@ -48,6 +48,8 @@ > #define GICD_ICFGR1 (0xC04) > #define GICD_ICFGR2 (0xC08) > #define GICD_ICFGRN (0xCFC) > +#define GICD_IGRPMODR (0xD00) > +#define GICD_IGRPMODRN (0xD7C) These registers are GICv3 specific and as such should be defined in arch/arm/include/asm/gic_v3_defs.h. ~Michal
On 19/10/2022 16:49, Michal Orzel wrote: > Hi Ayan, Hi Michal, > > On 19/10/2022 16:36, Ayan Kumar Halder wrote: >> >> Refer GIC v3 specification (Arm IHI 0069H ID020922), IGRPMODR (similar to >> IGROUPR) is relevant only when the guests run in secure/non-secure mode. >> As Xen does not implement security extensions for guests, so the registers >> are emulated as read as zero/write ignore. >> >> Signed-off-by: Ayan Kumar Halder <ayankuma@amd.com> >> --- >> >> Observed the issue while running Zephyr on R52. >> Also, found that KVM has similar behaviour. >> >> xen/arch/arm/include/asm/gic.h | 2 ++ >> xen/arch/arm/vgic-v3.c | 4 ++++ >> 2 files changed, 6 insertions(+) >> >> diff --git a/xen/arch/arm/include/asm/gic.h b/xen/arch/arm/include/asm/gic.h >> index 76e3fa5dc4..998dd62651 100644 >> --- a/xen/arch/arm/include/asm/gic.h >> +++ b/xen/arch/arm/include/asm/gic.h >> @@ -48,6 +48,8 @@ >> #define GICD_ICFGR1 (0xC04) >> #define GICD_ICFGR2 (0xC08) >> #define GICD_ICFGRN (0xCFC) >> +#define GICD_IGRPMODR (0xD00) >> +#define GICD_IGRPMODRN (0xD7C) > These registers are GICv3 specific and as such should be defined > in arch/arm/include/asm/gic_v3_defs.h. Thanks for pointing out. I have fixed this in v2. - Ayan > > ~Michal
diff --git a/xen/arch/arm/include/asm/gic.h b/xen/arch/arm/include/asm/gic.h index 76e3fa5dc4..998dd62651 100644 --- a/xen/arch/arm/include/asm/gic.h +++ b/xen/arch/arm/include/asm/gic.h @@ -48,6 +48,8 @@ #define GICD_ICFGR1 (0xC04) #define GICD_ICFGR2 (0xC08) #define GICD_ICFGRN (0xCFC) +#define GICD_IGRPMODR (0xD00) +#define GICD_IGRPMODRN (0xD7C) #define GICD_NSACR (0xE00) #define GICD_NSACRN (0xEFC) #define GICD_SGIR (0xF00) diff --git a/xen/arch/arm/vgic-v3.c b/xen/arch/arm/vgic-v3.c index 7fb99a9ff2..0c23f6df9d 100644 --- a/xen/arch/arm/vgic-v3.c +++ b/xen/arch/arm/vgic-v3.c @@ -685,6 +685,7 @@ static int __vgic_v3_distr_common_mmio_read(const char *name, struct vcpu *v, switch ( reg ) { case VRANGE32(GICD_IGROUPR, GICD_IGROUPRN): + case VRANGE32(GICD_IGRPMODR, GICD_IGRPMODRN): /* We do not implement security extensions for guests, read zero */ if ( dabt.size != DABT_WORD ) goto bad_width; goto read_as_zero; @@ -781,6 +782,7 @@ static int __vgic_v3_distr_common_mmio_write(const char *name, struct vcpu *v, switch ( reg ) { case VRANGE32(GICD_IGROUPR, GICD_IGROUPRN): + case VRANGE32(GICD_IGRPMODR, GICD_IGRPMODRN): /* We do not implement security extensions for guests, write ignore */ goto write_ignore_32; @@ -1192,6 +1194,7 @@ static int vgic_v3_distr_mmio_read(struct vcpu *v, mmio_info_t *info, case VRANGE32(GICD_ICACTIVER, GICD_ICACTIVERN): case VRANGE32(GICD_IPRIORITYR, GICD_IPRIORITYRN): case VRANGE32(GICD_ICFGR, GICD_ICFGRN): + case VRANGE32(GICD_IGRPMODR, GICD_IGRPMODRN): /* * Above all register are common with GICR and GICD * Manage in common @@ -1379,6 +1382,7 @@ static int vgic_v3_distr_mmio_write(struct vcpu *v, mmio_info_t *info, case VRANGE32(GICD_ICACTIVER, GICD_ICACTIVERN): case VRANGE32(GICD_IPRIORITYR, GICD_IPRIORITYRN): case VRANGE32(GICD_ICFGR, GICD_ICFGRN): + case VRANGE32(GICD_IGRPMODR, GICD_IGRPMODRN): /* Above registers are common with GICR and GICD * Manage in common */ return __vgic_v3_distr_common_mmio_write("vGICD", v, info,
Refer GIC v3 specification (Arm IHI 0069H ID020922), IGRPMODR (similar to IGROUPR) is relevant only when the guests run in secure/non-secure mode. As Xen does not implement security extensions for guests, so the registers are emulated as read as zero/write ignore. Signed-off-by: Ayan Kumar Halder <ayankuma@amd.com> --- Observed the issue while running Zephyr on R52. Also, found that KVM has similar behaviour. xen/arch/arm/include/asm/gic.h | 2 ++ xen/arch/arm/vgic-v3.c | 4 ++++ 2 files changed, 6 insertions(+)