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mx.microsoft.com 1; spf=temperror (sender ip is 165.204.84.17) smtp.rcpttodomain=lists.xenproject.org smtp.mailfrom=amd.com; dmarc=temperror action=none header.from=amd.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amd.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=gaPWf9DnJA/XGQug9i0zfhmL9v2rXPG9m6XEPCJ3yPc=; b=GPEVX+OhZAS3Dd4dNkt9pND2oXYMgO6EYNzKmHRX5930F4hN/6OzoF8xKw9zq6eS8OVL0EsLNjs5VCx3LyOra8cPdUqJlvmhAYH5UAFYfAE+o9e8l+MJkW+00cRZriMJHNFDBkag4HtHFN/2+kFC1AEzwKHZPJyW/eflnLbSh2s= X-MS-Exchange-Authentication-Results: spf=temperror (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=temperror action=none header.from=amd.com; Received-SPF: TempError (protection.outlook.com: error in processing during lookup of amd.com: DNS Timeout) From: Ayan Kumar Halder To: CC: , , , , , Ayan Kumar Halder Subject: [RFC PATCH v1 12/12] Arm: GICv3: Enable GICv3 for AArch32 Date: Fri, 21 Oct 2022 16:31:28 +0100 Message-ID: <20221021153128.44226-13-ayankuma@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20221021153128.44226-1-ayankuma@amd.com> References: <20221021153128.44226-1-ayankuma@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT019:EE_|BY5PR12MB4934:EE_ X-MS-Office365-Filtering-Correlation-Id: a17336cc-1fcf-465b-2cc7-08dab3797cab X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 21 Oct 2022 15:32:38.9885 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a17336cc-1fcf-465b-2cc7-08dab3797cab X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT019.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY5PR12MB4934 Refer ARM DDI 0487G.b ID072021, D13.2.86 - ID_PFR1_EL1, AArch32 Processor Feature Register 1 GIC, bits[31:28] == 0b0001 for GIC3.0 on Aarch32 One can now enable GICv3 on AArch32 systems. Signed-off-by: Ayan Kumar Halder --- xen/arch/arm/Kconfig | 2 +- xen/arch/arm/include/asm/cpufeature.h | 1 + 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/xen/arch/arm/Kconfig b/xen/arch/arm/Kconfig index 1fe5faf847..5eaf21b8e0 100644 --- a/xen/arch/arm/Kconfig +++ b/xen/arch/arm/Kconfig @@ -41,7 +41,7 @@ config ARM_EFI config GICV3 bool "GICv3 driver" - depends on ARM_64 && !NEW_VGIC + depends on (ARM_64 || ARM_32) && !NEW_VGIC default y ---help--- diff --git a/xen/arch/arm/include/asm/cpufeature.h b/xen/arch/arm/include/asm/cpufeature.h index c86a2e7f29..c8ca09d1c3 100644 --- a/xen/arch/arm/include/asm/cpufeature.h +++ b/xen/arch/arm/include/asm/cpufeature.h @@ -31,6 +31,7 @@ #define cpu_has_jazelle (boot_cpu_feature32(jazelle) > 0) #define cpu_has_thumbee (boot_cpu_feature32(thumbee) == 1) #define cpu_has_aarch32 (cpu_has_arm || cpu_has_thumb) +#define cpu_has_gicv3 (boot_cpu_feature32(gic) >= 1) #ifdef CONFIG_ARM_32 #define cpu_has_gentimer (boot_cpu_feature32(gentimer) == 1)