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pr=C From: Ayan Kumar Halder To: CC: , , , , , Ayan Kumar Halder Subject: [RFC PATCH v1 05/12] Arm: GICv3: Emulate GICR_PENDBASER and GICR_PROPBASER on AArch32 Date: Fri, 21 Oct 2022 16:31:21 +0100 Message-ID: <20221021153128.44226-6-ayankuma@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20221021153128.44226-1-ayankuma@amd.com> References: <20221021153128.44226-1-ayankuma@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT004:EE_|DM4PR12MB5343:EE_ X-MS-Office365-Filtering-Correlation-Id: 0df10cb3-4e2d-421b-79bb-08dab3796c6e X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: l9GOfyapDhb4HMYPkXnT60+LCACh8lYXr2DoeXX57VFfW1/K18LQVYcyDu2Q/zBG3cG/azTDXpXcpcMxTgmDMQVLtgFTMi47Icndmev5W106/5N5u7+c6GwRuBSCbZkcmMACR17WuN8irt/QqKQJtdgDkP4zu02HjV86WSGPQFCL76RnFzIdyts58q3hxFu3IIzU/WF8pJPuoW/u3s6Tn8aJdH1bMp6ZdaOMvzj6jZEvQ2l1Oyw+ChCYlsfFvcjkMStIBehX30/XxwcIw7U3FRz25nu3lqMEG18Q2wgzgK8cxEw58bD4MnApS66iJt7zvTMUggr0cerpEJxNXso63TdrwcH+rDjqdPR+CzJmBQs24luNrddOMoQecNEFZ1S6IoAEClVpVMrJNRWSi17LMtwv26zu2qVjkNSRpfud6AkCEidjMTnQ+v7ohHTWfC0GQrbWIQ5pSVRud7OHOPymlT03v6s0CBomzl5oSf0G09P0B8bEHXlzi5F4Q/tVkd+bPlh/RRn35uaPaJIhd3KA6dsRlvvM2zA1WWn6o4PLA2uErOC4msSeYxNDzC3hrMLR/I8RQVLR11VWXghOhEodT9fhb944p2qcIfEihffAA1T7oUvWaO7bGxlSszez6Fy6f4xxb9kH/yS7C5oxNyeIkad/njt9Uvf81P7K8eHbwPeKEdrzL8lkEsCLt/Ba6+k18YpzQv+ddJLWiBdLtuZ/IqJoxg+8mEs0ZgiT6dnMi+oA77hL0/i5ruNzSHDAH3WzkRelGcmaREb1M9P92oVLArqW5+hVPLaWAe0g1mG3vmd5tnT8kE7vcKPbtQNu13FS X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB03.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230022)(4636009)(39860400002)(346002)(396003)(136003)(376002)(451199015)(36840700001)(46966006)(40470700004)(41300700001)(2906002)(356005)(47076005)(186003)(83380400001)(26005)(2616005)(81166007)(82740400003)(5660300002)(426003)(1076003)(8936002)(82310400005)(8676002)(40460700003)(40480700001)(336012)(478600001)(70586007)(6666004)(4326008)(54906003)(70206006)(316002)(36756003)(6916009)(36860700001)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 21 Oct 2022 15:32:11.7628 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 0df10cb3-4e2d-421b-79bb-08dab3796c6e X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT004.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB5343 'unsigned long long' is defined as 64 bit across both aarch32 and aarch64. So, use 'ULL' for 64 bit word instead of UL which is 32 bits for aarch32. GICR_PENDBASER and GICR_PROPBASER both are 64 bit registers. Signed-off-by: Ayan Kumar Halder --- xen/arch/arm/include/asm/gic_v3_defs.h | 16 ++++++++-------- xen/arch/arm/vgic-v3.c | 6 ++++-- 2 files changed, 12 insertions(+), 10 deletions(-) diff --git a/xen/arch/arm/include/asm/gic_v3_defs.h b/xen/arch/arm/include/asm/gic_v3_defs.h index 728e28d5e5..48a1bc401e 100644 --- a/xen/arch/arm/include/asm/gic_v3_defs.h +++ b/xen/arch/arm/include/asm/gic_v3_defs.h @@ -134,15 +134,15 @@ #define GICR_PROPBASER_OUTER_CACHEABILITY_SHIFT 56 #define GICR_PROPBASER_OUTER_CACHEABILITY_MASK \ - (7UL << GICR_PROPBASER_OUTER_CACHEABILITY_SHIFT) + (7ULL << GICR_PROPBASER_OUTER_CACHEABILITY_SHIFT) #define GICR_PROPBASER_SHAREABILITY_SHIFT 10 #define GICR_PROPBASER_SHAREABILITY_MASK \ - (3UL << GICR_PROPBASER_SHAREABILITY_SHIFT) + (3ULL << GICR_PROPBASER_SHAREABILITY_SHIFT) #define GICR_PROPBASER_INNER_CACHEABILITY_SHIFT 7 #define GICR_PROPBASER_INNER_CACHEABILITY_MASK \ - (7UL << GICR_PROPBASER_INNER_CACHEABILITY_SHIFT) + (7ULL << GICR_PROPBASER_INNER_CACHEABILITY_SHIFT) #define GICR_PROPBASER_RES0_MASK \ - (GENMASK(63, 59) | GENMASK(55, 52) | GENMASK(6, 5)) + (GENMASK_ULL(63, 59) | GENMASK_ULL(55, 52) | GENMASK_ULL(6, 5)) #define GICR_PENDBASER_SHAREABILITY_SHIFT 10 #define GICR_PENDBASER_INNER_CACHEABILITY_SHIFT 7 @@ -152,11 +152,11 @@ #define GICR_PENDBASER_INNER_CACHEABILITY_MASK \ (7UL << GICR_PENDBASER_INNER_CACHEABILITY_SHIFT) #define GICR_PENDBASER_OUTER_CACHEABILITY_MASK \ - (7UL << GICR_PENDBASER_OUTER_CACHEABILITY_SHIFT) -#define GICR_PENDBASER_PTZ BIT(62, UL) + (7ULL << GICR_PENDBASER_OUTER_CACHEABILITY_SHIFT) +#define GICR_PENDBASER_PTZ BIT(62, ULL) #define GICR_PENDBASER_RES0_MASK \ - (BIT(63, UL) | GENMASK(61, 59) | GENMASK(55, 52) | \ - GENMASK(15, 12) | GENMASK(6, 0)) + (BIT(63, ULL) | GENMASK_ULL(61, 59) | GENMASK_ULL(55, 52) | \ + GENMASK_ULL(15, 12) | GENMASK_ULL(6, 0)) #define DEFAULT_PMR_VALUE 0xff diff --git a/xen/arch/arm/vgic-v3.c b/xen/arch/arm/vgic-v3.c index d86b41a39f..9f31360f56 100644 --- a/xen/arch/arm/vgic-v3.c +++ b/xen/arch/arm/vgic-v3.c @@ -254,14 +254,16 @@ static int __vgic_v3_rdistr_rd_mmio_read(struct vcpu *v, mmio_info_t *info, case VREG64(GICR_PENDBASER): { unsigned long flags; + uint64_t value; if ( !v->domain->arch.vgic.has_its ) goto read_as_zero_64; if ( !vgic_reg64_check_access(dabt) ) goto bad_width; spin_lock_irqsave(&v->arch.vgic.lock, flags); - *r = vreg_reg64_extract(v->arch.vgic.rdist_pendbase, info); - *r &= ~GICR_PENDBASER_PTZ; /* WO, reads as 0 */ + value = v->arch.vgic.rdist_pendbase; + value &= ~GICR_PENDBASER_PTZ; /* WO, reads as 0 */ + *r = vreg_reg64_extract(value, info); spin_unlock_irqrestore(&v->arch.vgic.lock, flags); return 1; }