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pr=C From: Ayan Kumar Halder To: CC: , , , , , , Ayan Kumar Halder Subject: [XEN v2 11/12] xen/Arm: GICv3: Define macros to read/write 64 bit Date: Mon, 31 Oct 2022 15:13:25 +0000 Message-ID: <20221031151326.22634-12-ayankuma@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20221031151326.22634-1-ayankuma@amd.com> References: <20221031151326.22634-1-ayankuma@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT114:EE_|SJ1PR12MB6219:EE_ X-MS-Office365-Filtering-Correlation-Id: 817997c4-64d5-4f93-355f-08dabb529557 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: m4PCC5K6hhyznZfO+zO0ygAnQgAt+px1ZRTWOx9cBxJVifT8n2rD7kBxROJbNlNFE15FiBBfXLKiPfLEnkUGS0mI8O0z5YQPA7c6SvaBYZ58gsF39ZWAROquTF6YG5igIZE2NgGvlUz5TskZwY9ZnFbZALIk3QK20+NjqHQuu7VT7BdU/XTCi65uVwT9QY4YXYlXzTlTIP0WEwjxMAY7HxLwMr+rSEcTgE5hi7iQ30ZB/PD2bQiQKuCyppUi/lasgHgSqq1lRP1PAMXLba7eC8F+GcNuo52HvYcq8EzjJIGQdVEz3k767SMuK7x83Mh7PZ5M7A0PfJFPwe5iV3uqfwXQ+VREzUdqQjz96Hf2CcC0fxxqytoxNyCYcelGeXQ0keySbCxPEZACPyUNEYCEvnhkN+yro0oQt2uZCJisreC6Baapx1BvFiD2TKiP+qT1qJwmFbtzZEJDyFeN2G2RNcJ2opdGZd7fbzrTN76fxMGKDwmXrA5DmJoLB9fLelZchI8MPb4AAI2skk8DMnSGP0D6B1NSzPqmn4tBeY1Y/SFnOABBaMKk36fRs65qage2R9UrUxay8T33UHoih60zj1ZqdzfvhLOKhb6hBIJUPy6wEpRPnmkywbXLHqKl0MERf+8JH9zjMAM4lARYAEFXhGkTyKfMpp43VyxS9EiWYZablWCWv/1k3XpNNWzPnJF8iJJQ29FYR28aP4PlT+g+Qohc8XdPjAArOY99N4FydatLl8z0TL92yACfceR5SIuYFdM1TXSeYVFLt0dTl8x5ESPyiWLhaO5x+SqenP6jof7WjTb4uLWRPlv0aUXZdzP6 X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230022)(4636009)(39860400002)(346002)(376002)(396003)(136003)(451199015)(36840700001)(46966006)(40470700004)(82310400005)(70586007)(70206006)(8676002)(54906003)(316002)(6916009)(36860700001)(356005)(81166007)(83380400001)(2906002)(36756003)(478600001)(1076003)(8936002)(40480700001)(41300700001)(5660300002)(4326008)(336012)(2616005)(186003)(40460700003)(82740400003)(426003)(6666004)(47076005)(26005)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 31 Oct 2022 15:14:19.3110 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 817997c4-64d5-4f93-355f-08dabb529557 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT114.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ1PR12MB6219 Defined readq_relaxed()/writeq_relaxed() to read and write 64 bit regs. This uses ldrd/strd instructions. Signed-off-by: Ayan Kumar Halder --- Changes from :- v1 - 1. Use ldrd/strd for readq_relaxed()/writeq_relaxed(). 2. No need to use le64_to_cpu() as the returned byte order is already in cpu endianess. xen/arch/arm/include/asm/arm32/io.h | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/xen/arch/arm/include/asm/arm32/io.h b/xen/arch/arm/include/asm/arm32/io.h index 73a879e9fb..d9d19ad764 100644 --- a/xen/arch/arm/include/asm/arm32/io.h +++ b/xen/arch/arm/include/asm/arm32/io.h @@ -72,6 +72,22 @@ static inline u32 __raw_readl(const volatile void __iomem *addr) return val; } +static inline u64 __raw_readq(const volatile void __iomem *addr) +{ + u64 val; + asm volatile("ldrd %Q1, %R1, %0" + : "+Qo" (*(volatile u64 __force *)addr), + "=r" (val)); + return val; +} + +static inline void __raw_writeq(u64 val, const volatile void __iomem *addr) +{ + asm volatile("strd %Q1, %R1, %0" + : "+Q" (*(volatile u64 __force *)addr) + : "r" (val)); +} + #define __iormb() rmb() #define __iowmb() wmb() @@ -80,17 +96,22 @@ static inline u32 __raw_readl(const volatile void __iomem *addr) __raw_readw(c)); __r; }) #define readl_relaxed(c) ({ u32 __r = le32_to_cpu((__force __le32) \ __raw_readl(c)); __r; }) +#define readq_relaxed(c) ({ u64 __r = le64_to_cpu((__force __le64) \ + __raw_readq(c)); __r; }) #define writeb_relaxed(v,c) __raw_writeb(v,c) #define writew_relaxed(v,c) __raw_writew((__force u16) cpu_to_le16(v),c) #define writel_relaxed(v,c) __raw_writel((__force u32) cpu_to_le32(v),c) +#define writeq_relaxed(v,c) __raw_writeq((__force u64) cpu_to_le64(v),c) #define readb(c) ({ u8 __v = readb_relaxed(c); __iormb(); __v; }) #define readw(c) ({ u16 __v = readw_relaxed(c); __iormb(); __v; }) #define readl(c) ({ u32 __v = readl_relaxed(c); __iormb(); __v; }) +#define readq(c) ({ u64 __v = readq_relaxed(c); __iormb(); __v; }) #define writeb(v,c) ({ __iowmb(); writeb_relaxed(v,c); }) #define writew(v,c) ({ __iowmb(); writew_relaxed(v,c); }) #define writel(v,c) ({ __iowmb(); writel_relaxed(v,c); }) +#define writeq(v,c) ({ __iowmb(); writeq_relaxed(v,c); }) #endif /* _ARM_ARM32_IO_H */