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pr=C From: Ayan Kumar Halder To: CC: , , , , , , Ayan Kumar Halder Subject: [XEN v2 02/12] xen/Arm: GICv3: Move the macros to compute the affnity level to arm64/arm32 Date: Mon, 31 Oct 2022 15:13:16 +0000 Message-ID: <20221031151326.22634-3-ayankuma@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20221031151326.22634-1-ayankuma@amd.com> References: <20221031151326.22634-1-ayankuma@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT062:EE_|CH0PR12MB5172:EE_ X-MS-Office365-Filtering-Correlation-Id: 3810ea97-d708-4244-f7e8-08dabb5289de X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: mXatm7IFJ5qHFisGsuFJLLhHFwnaecEWyikHz1EFVtOose/YQ72RjaCW4nM+CXOhz0x2w/ysgztZL7V9s+7aRFylKW8tW629Txl0TNYrZCeAdnVR6Fn7phNM8RP3zy+cgsk+r3BcNQCWkFGw6lgtwcShcJ1I7/OZIyo6dAad7cm35J2Tv5RqzZB+35sixVLXazLQky/ggucVQNJE611X4WikNAuJIlJi8v6U/95T0KtLWThaOEO57lYbHxxcqiyL3Am35nc7ZEo9ERZN0otK3ABC5kNFTi+q/QsWWt2zuPROgcmOdNrgtybS/7ZT7EXRiPEDr0oVCjCpPa9itYXAIyzZdte2/LA+y9W+M8V7zqdGpKDuR06saiCVlNFT7iT+V1hlRIfeoYdXxjJWd7rx1h2yznqoGxd/a+2nJvzjD5moPBf3GAFDjvFzR3izCRp1daIoJVYx7ztEMjduGH/2uFKSLqDmjfGNOQSHlsS7AiHkqu+RG4MwuIACbnvoureDt3TQsj6M2M0DaiVkTyU4qzoC2dOnVfUjJhXvSjFCr5f8MTD+WCSHWm7cyW4d0MDpsC0AH+qoKCgbYX1PWaDXu2Yg9F/jbBUQk8lwtImSRy+E/6rKri+iS/ftYtcVaCkoVciBu5i3Lx/hB+4/k6Jkp/H++6pkSD3P4g8z/huyEXrvYGLQ9g/jtR/xO44OkmD9/2Fula/H9/lrQDYs/PFvXNTM5nOZIsdN1AbWHfWtBgpToX1p27kX6OZYqA8sS4IbFEES38GnUiY90AE3iktmDlcerhtPFp0aBd+bOmRZqCxY1L2g0SBJ0bjBaugtYqibrnTH8dja9VtQ/LsB6JHzfhAHtTbodiSDYiZ9Ef6s87yEi7p4NMFPj8DtQuNfHjuZ X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230022)(4636009)(376002)(39860400002)(396003)(346002)(136003)(451199015)(46966006)(40470700004)(36840700001)(82310400005)(36756003)(8936002)(6666004)(70586007)(4326008)(316002)(8676002)(966005)(36860700001)(70206006)(41300700001)(54906003)(6916009)(5660300002)(40480700001)(2906002)(81166007)(356005)(426003)(83380400001)(186003)(478600001)(40460700003)(1076003)(82740400003)(26005)(2616005)(336012)(47076005)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 31 Oct 2022 15:13:59.9900 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 3810ea97-d708-4244-f7e8-08dabb5289de X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT062.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH0PR12MB5172 Refer https://elixir.bootlin.com/linux/v6.1-rc1/source/arch/arm64/ \ include/asm/cputype.h#L14 , for the macros specific for arm64. Refer https://elixir.bootlin.com/linux/v6.1-rc1/source/arch/arm/include/ \ asm/cputype.h#L54 , for the macros specific for arm32. MPIDR_LEVEL_SHIFT() differs between 64 and 32 bit. For 64 bit :- aff_lev3 aff_lev2 aff_lev1 aff_lev0 |________|________|________|________|________| 40 32 24 16 8 0 For 32 bit :- aff_lev3 aff_lev2 aff_lev1 aff_lev0 |________|________|________|________| 32 24 16 8 0 Signed-off-by: Ayan Kumar Halder --- Changes from :- v1 - 1. Rearranged the macro defines so that the common code (between arm32 and arm64) is placed in "arm/include/asm/processor.h". xen/arch/arm/include/asm/arm32/processor.h | 5 +++++ xen/arch/arm/include/asm/arm64/processor.h | 8 ++++++++ xen/arch/arm/include/asm/processor.h | 6 ------ 3 files changed, 13 insertions(+), 6 deletions(-) diff --git a/xen/arch/arm/include/asm/arm32/processor.h b/xen/arch/arm/include/asm/arm32/processor.h index 4e679f3273..82aa7f8d9d 100644 --- a/xen/arch/arm/include/asm/arm32/processor.h +++ b/xen/arch/arm/include/asm/arm32/processor.h @@ -56,6 +56,11 @@ struct cpu_user_regs uint32_t pad1; /* Doubleword-align the user half of the frame */ }; +/* + * Macros to extract affinity level. Picked from kernel + */ +#define MPIDR_LEVEL_SHIFT(level) (MPIDR_LEVEL_BITS * (level)) + #endif #endif /* __ASM_ARM_ARM32_PROCESSOR_H */ diff --git a/xen/arch/arm/include/asm/arm64/processor.h b/xen/arch/arm/include/asm/arm64/processor.h index c749f80ad9..295483a9dd 100644 --- a/xen/arch/arm/include/asm/arm64/processor.h +++ b/xen/arch/arm/include/asm/arm64/processor.h @@ -84,6 +84,14 @@ struct cpu_user_regs uint64_t sp_el1, elr_el1; }; +/* + * Macros to extract affinity level. picked from kernel + */ +#define MPIDR_LEVEL_BITS_SHIFT 3 + +#define MPIDR_LEVEL_SHIFT(level) \ + (((1 << (level)) >> 1) << MPIDR_LEVEL_BITS_SHIFT) + #undef __DECL_REG #endif /* __ASSEMBLY__ */ diff --git a/xen/arch/arm/include/asm/processor.h b/xen/arch/arm/include/asm/processor.h index 1dd81d7d52..ecfb62bbbe 100644 --- a/xen/arch/arm/include/asm/processor.h +++ b/xen/arch/arm/include/asm/processor.h @@ -122,13 +122,7 @@ /* * Macros to extract affinity level. picked from kernel */ - -#define MPIDR_LEVEL_BITS_SHIFT 3 #define MPIDR_LEVEL_MASK ((1 << MPIDR_LEVEL_BITS) - 1) - -#define MPIDR_LEVEL_SHIFT(level) \ - (((1 << (level)) >> 1) << MPIDR_LEVEL_BITS_SHIFT) - #define MPIDR_AFFINITY_LEVEL(mpidr, level) \ (((mpidr) >> MPIDR_LEVEL_SHIFT(level)) & MPIDR_LEVEL_MASK)