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pr=C From: Ayan Kumar Halder To: CC: , , , , , , Ayan Kumar Halder Subject: [XEN v2 06/12] xen/Arm: vGICv3: Fix emulation of ICC_SGI1R on AArch32 Date: Mon, 31 Oct 2022 15:13:20 +0000 Message-ID: <20221031151326.22634-7-ayankuma@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20221031151326.22634-1-ayankuma@amd.com> References: <20221031151326.22634-1-ayankuma@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT009:EE_|MW4PR12MB5604:EE_ X-MS-Office365-Filtering-Correlation-Id: d3368698-a592-4bf3-fdba-08dabb528f1d X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: u2zsv+y3hAmCawjxYt94RzsDAytQR4BT5ImykO+zdI1E3ULKBltKQd/WbkXj9yORxH5BTlM69LXuY8tk+xrft47U39Q4hRVIMqVYQcVT0g3adhIpaBBYtjMN0kiU/GlTph7JShBIO/3MGzgWr3ovCS19YQZFTbcT8Ryd0hGGXxkxnTOTycUs5sp/WiTvOimvXikR+CVtv8+95EPlfmOMAV6jgDZqDkjdNgd0CsUKDX9u19PCRxN6zhWQ96oyk77RjD1Mf7C/AVGLVUuvK8m7I7iOkyINw//v4JhKzz1bc62COwHJzK0tvgjUtxz8HzkKHYf1JKnhajQ1HUsNkNe3QQ0jVAtYrE8VuaZv8UW3mNeE7z8EKiT1OZ49YpiMmEwRh7ZW0EtPd8LkuwMa9jD2cmX8/C59OITlfEWCIeA9a3A/v+9vNrcIg71twMTj4O0CXwJ7vitmWi0ViPccxGiKkl3xKowtnSiSv21muL+XqYhyCqCa8k98DHaaWFLuEkt2Tp79NOiToPY+l8fTAKhfnYeQKEotBz4JvMry+S9u9NYPwU06/UXr9fx/nCuA+XdoKIwPINAjD08s6S650lQukIMCb3vig2ZoXMpLsc+h2FGIvGmY9pEGYKV6TY9LcICvCqJAX6yOOoQjlVLl7PsNbh6xZt6AKsESNz2OviK0M07+ycHre1kU5nm5b0VZ0QOpC3DeZdKRAYcahncLe59tGPGXNurEmDBp2Kbns1KgkEoajcukABX49ljp6uxmHr204J0N2Q3YhnnJl/Ngy1ayb08MzEF0a00em9uhKn4symA= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230022)(4636009)(396003)(136003)(376002)(346002)(39860400002)(451199015)(46966006)(40470700004)(36840700001)(47076005)(426003)(8936002)(82740400003)(4326008)(83380400001)(5660300002)(4744005)(40460700003)(316002)(2906002)(36756003)(478600001)(70586007)(6666004)(40480700001)(6916009)(54906003)(82310400005)(2616005)(41300700001)(1076003)(336012)(186003)(356005)(26005)(81166007)(8676002)(70206006)(36860700001)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 31 Oct 2022 15:14:08.8853 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: d3368698-a592-4bf3-fdba-08dabb528f1d X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT009.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW4PR12MB5604 Refer Arm IHI 0069H ID020922, 12.5.23, ICC_SGI1R is a 64 bit register on Aarch32 systems. Thus, the prototype needs to change to reflect this. The reason being 'register_t' is defined as 'u32' on AArch32. Signed-off-by: Ayan Kumar Halder Reviewed-by: Michal Orzel Acked-by: Julien Grall --- Changes from :- v1 - 1. Updated the commit message. xen/arch/arm/vgic-v3.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/xen/arch/arm/vgic-v3.c b/xen/arch/arm/vgic-v3.c index e5e6f2c573..1bae76a1e1 100644 --- a/xen/arch/arm/vgic-v3.c +++ b/xen/arch/arm/vgic-v3.c @@ -1477,7 +1477,7 @@ write_reserved: return 1; } -static bool vgic_v3_to_sgi(struct vcpu *v, register_t sgir) +static bool vgic_v3_to_sgi(struct vcpu *v, uint64_t sgir) { int virq; int irqmode;