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pr=C From: Ayan Kumar Halder To: CC: , , , , , , Ayan Kumar Halder Subject: [XEN v2 08/12] xen/Arm: GICv3: Define ICH_AP0R and ICH_AP1R for AArch32 Date: Mon, 31 Oct 2022 15:13:22 +0000 Message-ID: <20221031151326.22634-9-ayankuma@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20221031151326.22634-1-ayankuma@amd.com> References: <20221031151326.22634-1-ayankuma@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1NAM11FT083:EE_|MN2PR12MB4269:EE_ X-MS-Office365-Filtering-Correlation-Id: 41a2843c-d5d2-4c25-76c8-08dabb52919b X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: LUy5XsyIYlw1JIDWF55/M47+iXBehf3BfeMvc22vii0DQSz4tplkBrcaVchEQnBlVxRdt8XS+tJZutIfSHy6nLyhHV9VScfWRwxQZq9kySd0Xp90pKQVuki+kFf3h1j1um13VQ3nqiInFw7tUjX1T8ilQ84iIoBaBsONcLbiM4CdB1jYLMZI0B1y9JXGTblh6od9wov1QLNscxbfIkNERdal/qiAsXIYef4NrbND+AzGhoHP0gQbw8X3djtytoHaUhnUyDQRwxt0hrgUoYnyeuMNDW4IkzXTulLxXqG7KcieX/CxZpggXKs+EJ2EJ/5n3Rp8moy/1NbSxnEWw3r2xMPdDJjaN3zt0M7sod0N8rRbm74wCba8i1Ke3ja7TJfz0+v/x88NOWjRhD29dlJ2RYVUmdBj8q+4TCH6t84MwuVtY4qw/wFJAQvBTuoE634WNFbko7r0DezHHk5YwmGxIt8hOf9xoCV+ulZPv8cyNjfRNF7OrZMZaNDDE1WV9vWWR8QAAHtt/Wd+8vbyQgic0M1OMqhBK/cEpYTZdZcJBeMFEP8Elvay0Hu5KXOUOaPqtjN/nEgT7/TGYZ7nzP/SpTr+AqVZqCEqEeNSlZ/JB5b8U9EqPeMMMQOAvKTocfClO46+XPr2adLfKJNoBausCCX64lKef3lQVWoxqQtQuzyJAl66KkJ7qHF2cdOkiTfuLlfKTFjNHzBr0RF4i5CXb8F1PUxGeyZaO9UnLGs0g4XMc5QvNSewU2s3d9soiVKdCKHALC8buEwBFzYdb09sJsW0+LeVjHkZWmj//yVIRLAtnEQPhX3guqeuxKEpeCO0 X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB03.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230022)(4636009)(376002)(39860400002)(136003)(346002)(396003)(451199015)(40470700004)(46966006)(36840700001)(478600001)(6666004)(82310400005)(316002)(54906003)(26005)(6916009)(40480700001)(36860700001)(82740400003)(47076005)(2616005)(336012)(186003)(1076003)(36756003)(83380400001)(356005)(81166007)(40460700003)(426003)(2906002)(4326008)(8676002)(70586007)(70206006)(41300700001)(8936002)(5660300002)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 31 Oct 2022 15:14:12.9381 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 41a2843c-d5d2-4c25-76c8-08dabb52919b X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT083.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR12MB4269 Refer "Arm IHI 0069H ID020922", 12.7.1 - Interrupt Controller Hyp Active Priorities Group0 Registers 0-3 12.7.2 - Interrupt Controller Hyp Active Priorities Group1 Registers 0-3 Signed-off-by: Ayan Kumar Halder Reviewed-by: Michal Orzel Acked-by: Julien Grall --- Changes from :- v1 - 1. Moved coproc register definition to asm/cpregs.h. xen/arch/arm/include/asm/arm32/sysregs.h | 1 - xen/arch/arm/include/asm/cpregs.h | 11 +++++++++++ 2 files changed, 11 insertions(+), 1 deletion(-) diff --git a/xen/arch/arm/include/asm/arm32/sysregs.h b/xen/arch/arm/include/asm/arm32/sysregs.h index 8a9a014bef..1b2915a526 100644 --- a/xen/arch/arm/include/asm/arm32/sysregs.h +++ b/xen/arch/arm/include/asm/arm32/sysregs.h @@ -81,7 +81,6 @@ /* MVFR2 is not defined on ARMv7 */ #define MVFR2_MAYBE_UNDEFINED - #endif /* __ASSEMBLY__ */ #endif /* __ASM_ARM_ARM32_SYSREGS_H */ diff --git a/xen/arch/arm/include/asm/cpregs.h b/xen/arch/arm/include/asm/cpregs.h index 4421dd49ac..bfabee0bc3 100644 --- a/xen/arch/arm/include/asm/cpregs.h +++ b/xen/arch/arm/include/asm/cpregs.h @@ -404,6 +404,17 @@ #define ICH_LRC14_EL2 __LRC8_EL2(6) #define ICH_LRC15_EL2 __LRC8_EL2(7) +#define __AP0Rx_EL2(x) ___CP32(p15,4,c12,c8,x) +#define ICH_AP0R0_EL2 __AP0Rx_EL2(0) +#define ICH_AP0R1_EL2 __AP0Rx_EL2(1) +#define ICH_AP0R2_EL2 __AP0Rx_EL2(2) +#define ICH_AP0R3_EL2 __AP0Rx_EL2(3) + +#define __AP1Rx_EL2(x) ___CP32(p15,4,c12,c9,x) +#define ICH_AP1R0_EL2 __AP1Rx_EL2(0) +#define ICH_AP1R1_EL2 __AP1Rx_EL2(1) +#define ICH_AP1R2_EL2 __AP1Rx_EL2(2) +#define ICH_AP1R3_EL2 __AP1Rx_EL2(3) #endif #endif