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pr=C From: Michal Orzel To: CC: Michal Orzel , Stefano Stabellini , Julien Grall , Bertrand Marquis , Volodymyr Babchuk Subject: [PATCH 3/3] xen/arm: Define WLEN_8 macro and use it in debug-pl011 Date: Fri, 18 Nov 2022 12:46:18 +0100 Message-ID: <20221118114618.20754-4-michal.orzel@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221118114618.20754-1-michal.orzel@amd.com> References: <20221118114618.20754-1-michal.orzel@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT095:EE_|BL1PR12MB5126:EE_ X-MS-Office365-Filtering-Correlation-Id: 85675678-a091-4d4a-4e0d-08dac95aa2a6 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: pNksFMQiXPYjvVMFm33YJBM7/WKHf8VoBaEal+lXK6vZ1h9PHbeSs+xTVZ+U1+CfnwYBpkccvRw3nLx9yd9I/ieHA9NHtIcsF8tBuIOPjZpTt0Cz5qN/H84JnTWDt3OSR5GxShWZ/VLEsunKeSUNLtXL+ho/gdT0DtXDIs7sY2bE0FyQby2AxV27lgDjNyxCORd1pL06a741OBgONz/JZOhLH6jTe47S7BL85gnV0+6KPCs+u/vQHNjwVhSDThD2c7KKZ2QrIVhAMltwTjXXTBNIY9IMQOY8sVOkwIojGOtO6VdEv1zKS//uxYHwwDeRQX0I+UzGDovrpxozZMMNUbWn95lYWC2N/xPGApDvXTmNNpnC9PSWwHGAHn9mutjOOhu2c4L0K12+fv1G23TXtB7aYKog41USGwIHC268GVCfZVD6NBUNpRsJ4gfncfI7271mcg5gbBHgQuFNUDxWdwtWNoP0fcoJZBjnmZADcyZXVPQQqoxAONIqgAEQpEyALW5zjc9Tgbgcf/E1q1sdSxrAd3l53OyFs8fgOV8F4/RdibCvzbpfd2QzTL8lD93yC7VPfHOlCSE0TmtS6wmZh+9r1OfrvXntzHRl3UTDSjzyqhNkXPVrea92In0aurIy/p0pH+JcRlL9OoyEOSIiwX48zy0JVgoT1/SoDAkmn2p2cwdHOE2XBb/q8CRglyS6REK+MHY8R/dIA90gEQwC6rgQsQQxZ+P16laihcD+06E= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230022)(4636009)(346002)(396003)(39860400002)(376002)(136003)(451199015)(46966006)(36840700001)(40470700004)(41300700001)(36756003)(2616005)(36860700001)(1076003)(86362001)(2906002)(5660300002)(44832011)(336012)(426003)(83380400001)(186003)(8936002)(82740400003)(40460700003)(82310400005)(40480700001)(356005)(81166007)(47076005)(26005)(316002)(54906003)(6916009)(478600001)(6666004)(70586007)(70206006)(4326008)(8676002)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Nov 2022 11:47:13.8769 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 85675678-a091-4d4a-4e0d-08dac95aa2a6 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT095.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL1PR12MB5126 At the moment, early printk code for pl011 uses a hardcoded value for 8n1 LCR configuration. Define and use macro WLEN_8 for that purpose (no parity and 1 stop bit are defined as 0). Signed-off-by: Michal Orzel Acked-by: Julien Grall --- xen/arch/arm/arm32/debug-pl011.inc | 2 +- xen/arch/arm/arm64/debug-pl011.inc | 2 +- xen/arch/arm/include/asm/pl011-uart.h | 1 + 3 files changed, 3 insertions(+), 2 deletions(-) diff --git a/xen/arch/arm/arm32/debug-pl011.inc b/xen/arch/arm/arm32/debug-pl011.inc index 214f68dc95bd..c527f1d4424d 100644 --- a/xen/arch/arm/arm32/debug-pl011.inc +++ b/xen/arch/arm/arm32/debug-pl011.inc @@ -29,7 +29,7 @@ str \rc, [\rb, #FBRD] /* -> UARTFBRD (Baud divisor fraction) */ mov \rc, #(7372800 / CONFIG_EARLY_UART_PL011_BAUD_RATE / 16) str \rc, [\rb, #IBRD] /* -> UARTIBRD (Baud divisor integer) */ - mov \rc, #0x60 /* 8n1 */ + mov \rc, #WLEN_8 /* 8n1 */ str \rc, [\rb, #LCR_H] /* -> UARTLCR_H (Line control) */ ldr \rc, =(RXE | TXE | UARTEN) /* RXE | TXE | UARTEN */ str \rc, [\rb, #CR] /* -> UARTCR (Control Register) */ diff --git a/xen/arch/arm/arm64/debug-pl011.inc b/xen/arch/arm/arm64/debug-pl011.inc index d82f2f1de197..6d60e78c8ba3 100644 --- a/xen/arch/arm/arm64/debug-pl011.inc +++ b/xen/arch/arm/arm64/debug-pl011.inc @@ -28,7 +28,7 @@ strh w\c, [\xb, #FBRD] /* -> UARTFBRD (Baud divisor fraction) */ mov x\c, #(7372800 / CONFIG_EARLY_UART_PL011_BAUD_RATE / 16) strh w\c, [\xb, #IBRD] /* -> UARTIBRD (Baud divisor integer) */ - mov x\c, #0x60 /* 8n1 */ + mov x\c, #WLEN_8 /* 8n1 */ str w\c, [\xb, #LCR_H] /* -> UARTLCR_H (Line control) */ ldr x\c, =(RXE | TXE | UARTEN) str w\c, [\xb, #CR] /* -> UARTCR (Control Register) */ diff --git a/xen/arch/arm/include/asm/pl011-uart.h b/xen/arch/arm/include/asm/pl011-uart.h index 57e9ec73ac19..5bb563ec0814 100644 --- a/xen/arch/arm/include/asm/pl011-uart.h +++ b/xen/arch/arm/include/asm/pl011-uart.h @@ -55,6 +55,7 @@ /* LCR_H bits */ #define SPS (1<<7) /* Stick parity select */ +#define WLEN_8 (_AC(0x3, U) << 5) /* 8 bits word length */ #define FEN (1<<4) /* FIFO enable */ #define STP2 (1<<3) /* Two stop bits select */ #define EPS (1<<2) /* Even parity select */