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pr=C From: Ayan Kumar Halder To: CC: , , , , , , , , "Ayan Kumar Halder" Subject: [XEN v4 11/11] xen/Arm: GICv3: Enable GICv3 for AArch32 Date: Mon, 28 Nov 2022 15:56:49 +0000 Message-ID: <20221128155649.31386-12-ayan.kumar.halder@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20221128155649.31386-1-ayan.kumar.halder@amd.com> References: <20221128155649.31386-1-ayan.kumar.halder@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT039:EE_|PH7PR12MB6763:EE_ X-MS-Office365-Filtering-Correlation-Id: 7f6de3ce-d86f-4be6-7ea7-08dad1595a2f X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: N3XnHb5ypUHskx86nuoIycheq9vw0svu0UNkbNi6VFVcaroOEWoJWZjnOgLE2fSiUaHB23XkTBDFp/XsE/Mzd8RlHrX3oOiiNr9c4LgjsY/2l/BolOkUqRNLpxSPffmNj79zBMMcJdMjqp7UhSOeVLS0R3+3AN4AbyEfzPu0vOwjndbJJ6/B/lD6u4ZX3C7TGtMtWYkjoyuDzo11CnezeIdQQyocTeY/kjVQkinWyf7kposbRoB3b9aP/shW9Sp+uKPPehbhWhI6CUo2n22U/t3BfQKApM7KdYiPmcloKfgE7Ybl+Pq+DgYNpRPCK3cT2lxsM3rRImwe8M1facZNQLwbemaVaMz7mlzWJykTMpcgcbo56uBOLmOhkA0n9lyzFR2KReJKsd1NRpx5rdVXHJDByRTLHdfj6TooJtJdLm8+K2XiBxXhl1tOKDyFkhWULGUL6Gsv+g7h77ZzXTtkyxYkv31IWtbc9YF/43E69io5Rm8+UUI5EwcsvQpVTY/KBhlyb4PPR2UCDjEHB+amsxhpJeazcDUabv9b4iNhtrIp10Jhp1MumJMYzZ0xO2HxaMBOtf9FkxMwbrHg6y1BDXdQOaxKBoKR8p0tTDx6gnZvCzOsB4jUrMQkz3mUM47YviD9wI2Ul8IhpozUADWMwuNW8gmCQZGZyAmpvWFVb6NYjO8bp6dTegF/cdmgPFpGcMmqXZQ8l5s5an1fdSbKEoxWp7yYrHY989XnZESX7r4= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB03.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230022)(4636009)(136003)(39860400002)(346002)(396003)(376002)(451199015)(46966006)(40470700004)(36840700001)(36756003)(82740400003)(356005)(82310400005)(81166007)(40480700001)(26005)(478600001)(6666004)(41300700001)(70206006)(70586007)(8676002)(40460700003)(86362001)(4326008)(316002)(54906003)(6916009)(5660300002)(103116003)(8936002)(186003)(336012)(426003)(47076005)(2616005)(1076003)(83380400001)(36860700001)(2906002)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 28 Nov 2022 15:58:12.1234 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 7f6de3ce-d86f-4be6-7ea7-08dad1595a2f X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT039.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB6763 One can now use GICv3 on AArch32 systems. However, ITS is not supported. The reason being currently we are trying to validate GICv3 on an AArch32_v8R system. Refer ARM DDI 0568A.c ID110520, B1.3.1, "A Generic Interrupt Controller (GIC) implemented with an Armv8-R PE must not implement LPI support." By default GICv3 is disabled on AArch32 and enabled on AArch64. Updated SUPPORT.md to state that GICv3 on Arm32 is not security supported. Signed-off-by: Ayan Kumar Halder Reviewed-by: Michal Orzel --- Changed from :- v1 - 1. Remove "ARM_64 || ARM_32" as it is always true. 2. Updated SUPPORT.md. v2 - 1. GICv3 is enabled by default only on ARM_64. 2. Updated SUPPORT.md. v3 - 1. GICv3 is not selected by ARM_64. Rather, it is optionally enabled. 2. GICv3 is disabled by default on ARM_32. SUPPORT.md | 7 +++++++ xen/arch/arm/Kconfig | 9 +++++---- xen/arch/arm/include/asm/cpufeature.h | 1 + 3 files changed, 13 insertions(+), 4 deletions(-) diff --git a/SUPPORT.md b/SUPPORT.md index ab71464cf6..295369998e 100644 --- a/SUPPORT.md +++ b/SUPPORT.md @@ -76,6 +76,13 @@ For the Cortex A57 r0p0 - r1p1, see Errata 832075. Status, ARM SMMUv3: Tech Preview Status, Renesas IPMMU-VMSA: Supported, not security supported +### ARM/GICv3 + +GICv3 is an interrupt controller specification designed by Arm. + + Status, Arm64: Security supported + Status, Arm32: Supported, not security supported + ### ARM/GICv3 ITS Extension to the GICv3 interrupt controller to support MSI. diff --git a/xen/arch/arm/Kconfig b/xen/arch/arm/Kconfig index 52a05f704d..9d0c45f892 100644 --- a/xen/arch/arm/Kconfig +++ b/xen/arch/arm/Kconfig @@ -41,16 +41,17 @@ config ARM_EFI config GICV3 bool "GICv3 driver" - depends on ARM_64 && !NEW_VGIC - default y + depends on !NEW_VGIC + default n if ARM_32 + default y if ARM_64 ---help--- Driver for the ARM Generic Interrupt Controller v3. - If unsure, say Y + If unsure, say N for ARM_32 and Y for ARM_64 config HAS_ITS bool "GICv3 ITS MSI controller support (UNSUPPORTED)" if UNSUPPORTED - depends on GICV3 && !NEW_VGIC + depends on GICV3 && !NEW_VGIC && !ARM_32 config HVM def_bool y diff --git a/xen/arch/arm/include/asm/cpufeature.h b/xen/arch/arm/include/asm/cpufeature.h index c86a2e7f29..c62cf6293f 100644 --- a/xen/arch/arm/include/asm/cpufeature.h +++ b/xen/arch/arm/include/asm/cpufeature.h @@ -33,6 +33,7 @@ #define cpu_has_aarch32 (cpu_has_arm || cpu_has_thumb) #ifdef CONFIG_ARM_32 +#define cpu_has_gicv3 (boot_cpu_feature32(gic) >= 1) #define cpu_has_gentimer (boot_cpu_feature32(gentimer) == 1) /* * On Armv7, the value 0 is used to indicate that PMUv2 is not