From patchwork Mon Dec 12 09:55:13 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 13070884 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 088B2C4332F for ; Mon, 12 Dec 2022 09:55:46 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.459264.717025 (Exim 4.92) (envelope-from ) id 1p4fX7-00059g-Uv; Mon, 12 Dec 2022 09:55:37 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 459264.717025; Mon, 12 Dec 2022 09:55:37 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1p4fX7-00058D-MC; Mon, 12 Dec 2022 09:55:37 +0000 Received: by outflank-mailman (input) for mailman id 459264; Mon, 12 Dec 2022 09:55:36 +0000 Received: from mail.xenproject.org ([104.130.215.37]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1p4fX6-0004ja-3g for xen-devel@lists.xenproject.org; Mon, 12 Dec 2022 09:55:36 +0000 Received: from xenbits.xenproject.org ([104.239.192.120]) by mail.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1p4fX5-0001TW-Tg; Mon, 12 Dec 2022 09:55:35 +0000 Received: from 54-240-197-224.amazon.com ([54.240.197.224] helo=dev-dsk-jgrall-1b-035652ec.eu-west-1.amazon.com) by xenbits.xenproject.org with esmtpsa (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.92) (envelope-from ) id 1p4fX5-0001lz-MN; Mon, 12 Dec 2022 09:55:35 +0000 X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=xen.org; s=20200302mail; h=Content-Transfer-Encoding:MIME-Version:References: In-Reply-To:Message-Id:Date:Subject:Cc:To:From; bh=IkfkOtBPMDbEBtLpK7Qb9ilDR8TosDP0r588oIQO8sQ=; b=gFLykY5WKA9hd/5efzoUCsa14l koybqhFDNZ+bp+uwW0/nmTU0/J2tYNUB5XTQVCgobVsB6PZe5oJ0j8DZ1Ld3W8y5TUwCgjTwuXARF pIJJiOEXUcrwjXl+aH8djC1+w+0Q6xVY1qe9bf/TbbOwg3jHhZzI+BaqzgUV11BeGb/c=; From: Julien Grall To: xen-devel@lists.xenproject.org Cc: michal.orzel@amd.com, Luca.Fancellu@arm.com, Julien Grall , Stefano Stabellini , Julien Grall , Bertrand Marquis , Volodymyr Babchuk Subject: [PATCH v3 08/18] xen/arm32: head: Introduce an helper to flush the TLBs Date: Mon, 12 Dec 2022 09:55:13 +0000 Message-Id: <20221212095523.52683-9-julien@xen.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221212095523.52683-1-julien@xen.org> References: <20221212095523.52683-1-julien@xen.org> MIME-Version: 1.0 From: Julien Grall The sequence for flushing the TLBs is 4 instruction long and often requires an explanation how it works. So create an helper and use it in the boot code (switch_ttbr() is left alone for now). Note that in secondary_switched, we were also flushing the instruction cache and branch predictor. Neither of them was necessary because: * We are only supporting IVIPT cache on arm32, so the instruction cache flush is only necessary when executable code is modified. None of the boot code is doing that. * The instruction cache is not invalidated and misprediction is not a problem at boot. Signed-off-by: Julien Grall Reviewed-by: Michal Orzel --- Changes in v3: * Fix typo * Update the documentation * Rename the argument from tmp1 to tmp --- xen/arch/arm/arm32/head.S | 30 +++++++++++++++++------------- 1 file changed, 17 insertions(+), 13 deletions(-) diff --git a/xen/arch/arm/arm32/head.S b/xen/arch/arm/arm32/head.S index 40c1d7502007..315abbbaebec 100644 --- a/xen/arch/arm/arm32/head.S +++ b/xen/arch/arm/arm32/head.S @@ -66,6 +66,20 @@ add \rb, \rb, r10 .endm +/* + * Flush local TLBs + * + * @tmp: Scratch register + * + * See asm/arm32/flushtlb.h for the explanation of the sequence. + */ +.macro flush_xen_tlb_local tmp + dsb nshst + mcr CP32(\tmp, TLBIALLH) + dsb nsh + isb +.endm + /* * Common register usage in this file: * r0 - @@ -232,11 +246,7 @@ secondary_switched: mcrr CP64(r4, r5, HTTBR) dsb isb - mcr CP32(r0, TLBIALLH) /* Flush hypervisor TLB */ - mcr CP32(r0, ICIALLU) /* Flush I-cache */ - mcr CP32(r0, BPIALL) /* Flush branch predictor */ - dsb /* Ensure completion of TLB+BP flush */ - isb + flush_xen_tlb_local r0 #ifdef CONFIG_EARLY_PRINTK /* Use a virtual address to access the UART. */ @@ -529,8 +539,7 @@ enable_mmu: * The state of the TLBs is unknown before turning on the MMU. * Flush them to avoid stale one. */ - mcr CP32(r0, TLBIALLH) /* Flush hypervisor TLBs */ - dsb nsh + flush_xen_tlb_local r0 /* Write Xen's PT's paddr into the HTTBR */ load_paddr r0, boot_pgtable @@ -605,12 +614,7 @@ remove_identity_mapping: strd r2, r3, [r0, r1] identity_mapping_removed: - /* See asm/arm32/flushtlb.h for the explanation of the sequence. */ - dsb nshst - mcr CP32(r0, TLBIALLH) - dsb nsh - isb - + flush_xen_tlb_local r0 mov pc, lr ENDPROC(remove_identity_mapping)