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pr=C From: Ayan Kumar Halder To: CC: , , , , , Ayan Kumar Halder Subject: [XEN v2 11/11] xen/arm: p2m: Enable support for 32bit IPA Date: Tue, 17 Jan 2023 17:43:58 +0000 Message-ID: <20230117174358.15344-12-ayan.kumar.halder@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230117174358.15344-1-ayan.kumar.halder@amd.com> References: <20230117174358.15344-1-ayan.kumar.halder@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL02EPF000108E9:EE_|MN0PR12MB6003:EE_ X-MS-Office365-Filtering-Correlation-Id: decc4f7b-83ff-4bc6-1c26-08daf8b29c2a X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: z8gaDb+q0YxsODVGSp4Qzyz0rZZ0aV8Er2c4KtZ1LLzKshoDeE5Cmrcjdk+jMis9w726fSVcuMPlJ5u8PGraQnqlChyv4wjRAzLUU/i1LawdYRQGxoZG905gHGbsWo3eEWpYspewdrvSe8GoztTQkJOVxuvrOKUp22PvQDJAsOaaGStxfhldGNut2kozWWffK5VZ6lseQUPBmKNFU8hzawo9O64tMH42wKBMcB1w3ZsIA9OnMTnCZDhgwcBEXRL++QRcutO/JauR5Asao6Yq0Kf+bW5x64H1alZC3tSp1SgGYLcGbJSmV6qfy+ThuI7i7w8ZL/dOLkRclpQMwGrYGoSQsoKFraqjIn9FoE/A4jmY0Q17CVAVXjkmW143z1e8rrLH3N93VzIxt4Ds4Hf9MVt5cqF6LpmLnvivtDqxW6cVyGY2WveRRzczBn54lo99VwBqucvOzkWvwPpeOmjmWCveBtpDZXQ0jQpYwMG6FgZv60mY1TCtlqGEe2Nm5mY3yEUENjKkTiuEX6Vb1MZYhZGibBwiGDx/N+y+d+aVqH3e1aIeXR6pToDYQKXg8P0x/JC4FM6IFdXjgr4wFqvQg9dajFVXptOKihVx3hIRCQ6V3OHgbW6iax+hEW2OGatJzwz2+1puRDdXLlFz2L3gOcBhoIeOvaAp9CvphoKWB6mvQMVzi75vdW4L9sIzVA6DWIXjaErOL4WiS+8XT8n2YkXPqehjpJxLRsREfxyBgt4= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230022)(4636009)(376002)(136003)(396003)(346002)(39860400002)(451199015)(46966006)(36840700001)(40470700004)(41300700001)(8936002)(36756003)(83380400001)(2616005)(70206006)(70586007)(6916009)(4326008)(47076005)(426003)(8676002)(336012)(54906003)(316002)(5660300002)(81166007)(356005)(82740400003)(82310400005)(86362001)(1076003)(2906002)(40460700003)(103116003)(36860700001)(40480700001)(478600001)(186003)(26005)(6666004)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Jan 2023 17:45:23.3593 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: decc4f7b-83ff-4bc6-1c26-08daf8b29c2a X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF000108E9.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN0PR12MB6003 VTCR.T0SZ should be set as 0x20 to support 32bit IPA. Refer ARM DDI 0487I.a ID081822, G8-9824, G8.2.171, VTCR, "Virtualization Translation Control Register" for the bit descriptions. Signed-off-by: Ayan Kumar Halder Acked-by: Stefano Stabellini --- Changes from - v1 - New patch. xen/arch/arm/p2m.c | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/xen/arch/arm/p2m.c b/xen/arch/arm/p2m.c index 948f199d84..cfdea55e71 100644 --- a/xen/arch/arm/p2m.c +++ b/xen/arch/arm/p2m.c @@ -2266,13 +2266,17 @@ void __init setup_virt_paging(void) register_t val = VTCR_RES1|VTCR_SH0_IS|VTCR_ORGN0_WBWA|VTCR_IRGN0_WBWA; #ifdef CONFIG_ARM_32 - if ( p2m_ipa_bits < 40 ) + if ( p2m_ipa_bits < PADDR_BITS ) panic("P2M: Not able to support %u-bit IPA at the moment\n", p2m_ipa_bits); - printk("P2M: 40-bit IPA\n"); - p2m_ipa_bits = 40; + printk("P2M: %u-bit IPA\n",PADDR_BITS); + p2m_ipa_bits = PADDR_BITS; +#ifdef CONFIG_ARM_PA_32 + val |= VTCR_T0SZ(0x20); /* 32 bit IPA */ +#else val |= VTCR_T0SZ(0x18); /* 40 bit IPA */ +#endif val |= VTCR_SL0(0x1); /* P2M starts at first level */ #else /* CONFIG_ARM_64 */ static const struct {