Message ID | 20230208120529.22313-10-ayan.kumar.halder@amd.com (mailing list archive) |
---|---|
State | Superseded |
Headers | show |
Series | Add support for 32 bit physical address | expand |
Hi Ayan, On 08/02/2023 12:05, Ayan Kumar Halder wrote: > VTCR.T0SZ should be set as 0x20 to support 32bit IPA. > Refer ARM DDI 0487I.a ID081822, G8-9824, G8.2.171, VTCR, > "Virtualization Translation Control Register" for the bit descriptions. > > Signed-off-by: Ayan Kumar Halder <ayan.kumar.halder@amd.com> > Acked-by: Stefano Stabellini <sstabellini@kernel.org> This will need a respin based on the discussion we had in v2. The main things are: - 32-bit IPA will be using one page at the root (not 2 like for 40-bit IPA) - the code should be consolidate with arm64 as the logic is mainly the same. Cheers,
diff --git a/xen/arch/arm/p2m.c b/xen/arch/arm/p2m.c index 948f199d84..cfdea55e71 100644 --- a/xen/arch/arm/p2m.c +++ b/xen/arch/arm/p2m.c @@ -2266,13 +2266,17 @@ void __init setup_virt_paging(void) register_t val = VTCR_RES1|VTCR_SH0_IS|VTCR_ORGN0_WBWA|VTCR_IRGN0_WBWA; #ifdef CONFIG_ARM_32 - if ( p2m_ipa_bits < 40 ) + if ( p2m_ipa_bits < PADDR_BITS ) panic("P2M: Not able to support %u-bit IPA at the moment\n", p2m_ipa_bits); - printk("P2M: 40-bit IPA\n"); - p2m_ipa_bits = 40; + printk("P2M: %u-bit IPA\n",PADDR_BITS); + p2m_ipa_bits = PADDR_BITS; +#ifdef CONFIG_ARM_PA_32 + val |= VTCR_T0SZ(0x20); /* 32 bit IPA */ +#else val |= VTCR_T0SZ(0x18); /* 40 bit IPA */ +#endif val |= VTCR_SL0(0x1); /* P2M starts at first level */ #else /* CONFIG_ARM_64 */ static const struct {