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pr=C From: Ayan Kumar Halder To: CC: , , , , , , , , , , Ayan Kumar Halder Subject: [XEN v3 5/9] xen/arm: smmu: Use writeq_relaxed_non_atomic() for writing to SMMU_CBn_TTBR0 Date: Wed, 8 Feb 2023 12:05:25 +0000 Message-ID: <20230208120529.22313-6-ayan.kumar.halder@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230208120529.22313-1-ayan.kumar.halder@amd.com> References: <20230208120529.22313-1-ayan.kumar.halder@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT068:EE_|SJ1PR12MB6220:EE_ X-MS-Office365-Filtering-Correlation-Id: eaf8e6d7-befb-4405-9b73-08db09ccdb67 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: zSfFdIJa0eWdbPTD+99ILui8bDnYvpqqY2IUK4OMN4UGkWqcyubtJomDr681hLGkOZ7ts+0rIThZU7XdRolW2m2JxELeyM2gY05HTPqj60m2AYTScUUXCgnDnSscvqMfCdGsYbZA9LBgvlm8TnIA7sKAwPlxNmlqsC49NSVIe7nq+QroTDuR9rG/strBHdET3cw0eMulzyznX0QQuwbSUzEeaIQqtq/2t9Cv2A6UdDs0pty18Ozel8Oo4KItd0aaEbulX/JoDqq5rMlQLdNyLMZ2TO0t/b5G2sVZF/KRd84+y1t8SDVbuR2WVxDvpgXYAyQXPD5SiqFIcrarFNFusCrpOpvKZTBKjNjjkRtBmc0GG2+rf5XObOyphY7bDdbXdJg2IFpvkVcjhWv2w5Chs5ICkyCVf5+RJ61g+RoU3Wn7a0HV/rPo6gZG8INd8ykphT/UHOyzE9RolrdHqHceStNiIFwgGz+hJhj2uoeiy3HUosPeGsMEHSN0Y5ti3rHtFfRZbAEfdKgU178j/8e9LwuGU+Eko2EbHy/AlflS34PEJN5kdKQfCySS7LjE0jvZexeNHNa4QpNlY+rbU4H7Epi1c7opqvrsXTZhuSu2mtvtg5F8Gk7kf8f59+KsrOdUt74f1iXzAIjgkVmItoToXMIezG4XNE8jdV4Lue2z8dtbotzPVqlJkewmkRSAWz3HeCdz/lzYSX6rAth40T6EH20mvaxov8iqT/9NIyHB5gQ= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB03.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230025)(4636009)(39860400002)(136003)(376002)(396003)(346002)(451199018)(36840700001)(46966006)(40470700004)(7416002)(36756003)(186003)(82740400003)(26005)(2616005)(81166007)(426003)(6666004)(47076005)(82310400005)(83380400001)(36860700001)(1076003)(336012)(70206006)(70586007)(103116003)(4326008)(6916009)(40460700003)(40480700001)(8936002)(5660300002)(41300700001)(8676002)(356005)(86362001)(54906003)(478600001)(316002)(2906002)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Feb 2023 12:06:06.1567 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: eaf8e6d7-befb-4405-9b73-08db09ccdb67 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT068.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ1PR12MB6220 Refer ARM IHI 0062D.c ID070116 (SMMU 2.0 spec), 17-360, 17.3.9, SMMU_CBn_TTBR0 is a 64 bit register. Thus, one can use writeq_relaxed_non_atomic() to write to it instead of invoking writel_relaxed() twice for lower half and upper half of the register. This also helps us as p2maddr is 'paddr_t' (which may be u32 in future). Thus, one can assign p2maddr to a 64 bit register and do the bit manipulations on it, to generate the value for SMMU_CBn_TTBR0. Signed-off-by: Ayan Kumar Halder Reviewed-by: Stefano Stabellini --- Changes from - v1 - 1. Extracted the patch from "[XEN v1 8/9] xen/arm: Other adaptations required to support 32bit paddr". Use writeq_relaxed_non_atomic() to write u64 register in a non-atomic fashion. v2 - 1. Added R-b. xen/drivers/passthrough/arm/smmu.c | 15 ++++++++------- 1 file changed, 8 insertions(+), 7 deletions(-) diff --git a/xen/drivers/passthrough/arm/smmu.c b/xen/drivers/passthrough/arm/smmu.c index 79281075ba..c8ef2a925f 100644 --- a/xen/drivers/passthrough/arm/smmu.c +++ b/xen/drivers/passthrough/arm/smmu.c @@ -499,8 +499,7 @@ enum arm_smmu_s2cr_privcfg { #define ARM_SMMU_CB_SCTLR 0x0 #define ARM_SMMU_CB_RESUME 0x8 #define ARM_SMMU_CB_TTBCR2 0x10 -#define ARM_SMMU_CB_TTBR0_LO 0x20 -#define ARM_SMMU_CB_TTBR0_HI 0x24 +#define ARM_SMMU_CB_TTBR0 0x20 #define ARM_SMMU_CB_TTBCR 0x30 #define ARM_SMMU_CB_S1_MAIR0 0x38 #define ARM_SMMU_CB_FSR 0x58 @@ -1083,6 +1082,7 @@ static void arm_smmu_flush_pgtable(struct arm_smmu_device *smmu, void *addr, static void arm_smmu_init_context_bank(struct arm_smmu_domain *smmu_domain) { u32 reg; + u64 reg64; bool stage1; struct arm_smmu_cfg *cfg = &smmu_domain->cfg; struct arm_smmu_device *smmu = smmu_domain->smmu; @@ -1177,12 +1177,13 @@ static void arm_smmu_init_context_bank(struct arm_smmu_domain *smmu_domain) dev_notice(smmu->dev, "d%u: p2maddr 0x%"PRIpaddr"\n", smmu_domain->cfg.domain->domain_id, p2maddr); - reg = (p2maddr & ((1ULL << 32) - 1)); - writel_relaxed(reg, cb_base + ARM_SMMU_CB_TTBR0_LO); - reg = (p2maddr >> 32); + reg64 = p2maddr; + if (stage1) - reg |= ARM_SMMU_CB_ASID(cfg) << TTBRn_HI_ASID_SHIFT; - writel_relaxed(reg, cb_base + ARM_SMMU_CB_TTBR0_HI); + reg64 |= (((uint64_t) (ARM_SMMU_CB_ASID(cfg) << TTBRn_HI_ASID_SHIFT)) + << 32); + + writeq_relaxed_non_atomic(reg64, cb_base + ARM_SMMU_CB_TTBR0); /* * TTBCR