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pr=C From: Ayan Kumar Halder To: CC: , , , , , , , , , , Ayan Kumar Halder Subject: [XEN v4 06/11] xen/arm: smmu: Use writeq_relaxed_non_atomic() for writing to SMMU_CBn_TTBR0 Date: Tue, 21 Mar 2023 14:03:52 +0000 Message-ID: <20230321140357.24094-7-ayan.kumar.halder@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230321140357.24094-1-ayan.kumar.halder@amd.com> References: <20230321140357.24094-1-ayan.kumar.halder@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS1PEPF0000B079:EE_|DS0PR12MB6415:EE_ X-MS-Office365-Filtering-Correlation-Id: 8f74f5e1-0f78-44d8-bd2f-08db2a154fc7 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: DkQet4KD9tM/vlmph+nkGnsmiH9mWPc4NxUcqsJbMNmkEd4ZT3jjs932in0GNf4f//xGdlqGYgoZmWC11y06m7EIL5agmypUJ7bn8k6GYE8oMVOj622nmH86jKZmM+B4Brod+Pu8ArS5+b9b+V4GA5eua+x1XwGB/7fNKCKHWMUYNkXkqUvdYA1cntAOsUTlIVO87E+VFZDK3a5D0y+ErAr6/g52gwwKpX0DNthaGYkeTDcYCT7d+IVY2sZPbFs0ll1CWXRL8crFMDVuDkVqTXZzCBNncChESLom+06w4zVuTe+/HEn/nT1bC8yNBZCUPgYsMhexPW8miDDMglMaeoI0YWPk5sFva4/kvtF8EmfErRysKl83d8O7TGDE8TxQtPND7++WXMsn5DMDRC+Opo091LpPaQ2CJsKVoHnmhTxAPL7MbzRbyiYCbiXOxTRwL/IHNp6UPs+QS+9ujzxo9YCLaf8woPuI2nkGu08cLMLzAd3KSxd5mdkA7kofYMK6JxfSb1XOLcuEPKeGSeaqB23HkI/3CLAaxH/QqKQZCVvwfQyg4MXNhYu9L2WJpCyAvw0JAKza7ZZdhApeN8PAIzyAiG1StWhxQsK74UWvD4ogSOr5259LQ5iWT0ACssSJFFavoZj5q8I9nUEd1UjiKNN26BU85MC15V796o8LQN7ad6Hw3E+sojFnPuv1UiMg8Gopd4Nz1gihg1ctqqgylnZ3mX14srpfJYr8nwUsbpo= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB03.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230025)(4636009)(136003)(39860400002)(376002)(346002)(396003)(451199018)(46966006)(36840700001)(40470700004)(41300700001)(7416002)(8936002)(5660300002)(4326008)(36860700001)(40480700001)(82310400005)(356005)(103116003)(86362001)(36756003)(40460700003)(81166007)(82740400003)(2906002)(6666004)(336012)(83380400001)(426003)(47076005)(478600001)(2616005)(26005)(186003)(1076003)(54906003)(316002)(70586007)(6916009)(70206006)(8676002)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 21 Mar 2023 14:05:22.3289 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 8f74f5e1-0f78-44d8-bd2f-08db2a154fc7 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DS1PEPF0000B079.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB6415 Refer ARM IHI 0062D.c ID070116 (SMMU 2.0 spec), 17-360, 17.3.9, SMMU_CBn_TTBR0 is a 64 bit register. Thus, one can use writeq_relaxed_non_atomic() to write to it instead of invoking writel_relaxed() twice for lower half and upper half of the register. This also helps us as p2maddr is 'paddr_t' (which may be u32 in future). Thus, one can assign p2maddr to a 64 bit register and do the bit manipulations on it, to generate the value for SMMU_CBn_TTBR0. Reviewed-by: Stefano Stabellini Signed-off-by: Ayan Kumar Halder --- Changes from - v1 - 1. Extracted the patch from "[XEN v1 8/9] xen/arm: Other adaptations required to support 32bit paddr". Use writeq_relaxed_non_atomic() to write u64 register in a non-atomic fashion. v2 - 1. Added R-b. v3 - 1. No changes. xen/drivers/passthrough/arm/smmu.c | 15 ++++++++------- 1 file changed, 8 insertions(+), 7 deletions(-) diff --git a/xen/drivers/passthrough/arm/smmu.c b/xen/drivers/passthrough/arm/smmu.c index 79281075ba..c8ef2a925f 100644 --- a/xen/drivers/passthrough/arm/smmu.c +++ b/xen/drivers/passthrough/arm/smmu.c @@ -499,8 +499,7 @@ enum arm_smmu_s2cr_privcfg { #define ARM_SMMU_CB_SCTLR 0x0 #define ARM_SMMU_CB_RESUME 0x8 #define ARM_SMMU_CB_TTBCR2 0x10 -#define ARM_SMMU_CB_TTBR0_LO 0x20 -#define ARM_SMMU_CB_TTBR0_HI 0x24 +#define ARM_SMMU_CB_TTBR0 0x20 #define ARM_SMMU_CB_TTBCR 0x30 #define ARM_SMMU_CB_S1_MAIR0 0x38 #define ARM_SMMU_CB_FSR 0x58 @@ -1083,6 +1082,7 @@ static void arm_smmu_flush_pgtable(struct arm_smmu_device *smmu, void *addr, static void arm_smmu_init_context_bank(struct arm_smmu_domain *smmu_domain) { u32 reg; + u64 reg64; bool stage1; struct arm_smmu_cfg *cfg = &smmu_domain->cfg; struct arm_smmu_device *smmu = smmu_domain->smmu; @@ -1177,12 +1177,13 @@ static void arm_smmu_init_context_bank(struct arm_smmu_domain *smmu_domain) dev_notice(smmu->dev, "d%u: p2maddr 0x%"PRIpaddr"\n", smmu_domain->cfg.domain->domain_id, p2maddr); - reg = (p2maddr & ((1ULL << 32) - 1)); - writel_relaxed(reg, cb_base + ARM_SMMU_CB_TTBR0_LO); - reg = (p2maddr >> 32); + reg64 = p2maddr; + if (stage1) - reg |= ARM_SMMU_CB_ASID(cfg) << TTBRn_HI_ASID_SHIFT; - writel_relaxed(reg, cb_base + ARM_SMMU_CB_TTBR0_HI); + reg64 |= (((uint64_t) (ARM_SMMU_CB_ASID(cfg) << TTBRn_HI_ASID_SHIFT)) + << 32); + + writeq_relaxed_non_atomic(reg64, cb_base + ARM_SMMU_CB_TTBR0); /* * TTBCR