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pr=C From: Ayan Kumar Halder To: CC: , , , , , , , , , , Ayan Kumar Halder Subject: [XEN v4 08/11] xen/arm: guest_walk: LPAE specific bits should be enclosed within "ifndef CONFIG_PHYS_ADDR_T_32" Date: Tue, 21 Mar 2023 14:03:54 +0000 Message-ID: <20230321140357.24094-9-ayan.kumar.halder@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230321140357.24094-1-ayan.kumar.halder@amd.com> References: <20230321140357.24094-1-ayan.kumar.halder@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS1PEPF0000E654:EE_|DM6PR12MB4418:EE_ X-MS-Office365-Filtering-Correlation-Id: c6eedad3-5752-4a2e-a25d-08db2a15535c X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: CkiNa0e6jA+iwUsJ8pNb0VrmRzsXrTGXY0VVNugihxXXm+jVQW8GgoLHOktiJZiEGlVVRXckKStjw5X0rLvxlEtrBvceAiPVjY1Pu43FxgoUHpirdf6Rdbi8E3vjdv7nB43OXQ6QFP9jZa66qWF/TQ1qMsr0YKQLDpWG2xZoO4uHWwo//B4UZFkmxaCQ80cSXLwCcWBPbJ/iavbMTUfRdn2GofDh6pB3DjzHJd1d+fduJIza6eGHI94IP8Q7lbyiqlw2JN4C6utW9nSRtv/ejgQ4KbLH4I4YLfJMvHJuJ7UO81wCMScq392DcR2qmU4gqpQj71EEwMETYWsAFW22I+cwqW/9RYofOKDDQrMP6S084N5L1u4Uf29J4JdKyVHJ9noijBoGCXcehljV89seYiKEqnxGb6H6iOOsCPi6tTENOJW07Dm95yQMyastqQbplEepjgsC8v7T6464xr2DYTFZLuC1+xmoC+vd2cXZJXTj2UBoJUqsEqSrBZkxhFADK81I9PtrVVKgOdOreJ/fxzWE+sB3GMYj7qlbGSABaUCilff+heNtYhoeT9ZSAfXAawr553UIZ0CeFpZgfnMrjmGpwMr4Ru26A2YbD/Du032F4tXwTwellBCGojPdDE7z4Y8oQUDJFsk0dZwUc9rLn6s4rPKue6qcr36SE5FTWVnVBAB3QMUBQDCJ5SmdHkg4ynxy5OQ7emweg/jvvmi84HUK/XWx9PqUFe0qDcTrqaE= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230025)(4636009)(136003)(376002)(39860400002)(396003)(346002)(451199018)(40470700004)(36840700001)(46966006)(8936002)(5660300002)(7416002)(36860700001)(41300700001)(356005)(40480700001)(36756003)(82310400005)(103116003)(86362001)(82740400003)(40460700003)(81166007)(2906002)(4326008)(47076005)(426003)(186003)(336012)(83380400001)(6666004)(478600001)(2616005)(1076003)(54906003)(26005)(316002)(8676002)(70586007)(6916009)(70206006)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 21 Mar 2023 14:05:28.3380 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: c6eedad3-5752-4a2e-a25d-08db2a15535c X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DS1PEPF0000E654.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB4418 As the previous patch introduces CONFIG_PHYS_ADDR_T_32 to support 32 bit physical addresses, the code specific to "Large Physical Address Extension" (ie LPAE) should be enclosed within "ifndef CONFIG_PHYS_ADDR_T_32". Refer xen/arch/arm/include/asm/short-desc.h, "short_desc_l1_supersec_t" unsigned int extbase1:4; /* Extended base address, PA[35:32] */ unsigned int extbase2:4; /* Extended base address, PA[39:36] */ Thus, extbase1 and extbase2 are not valid when 32 bit physical addresses are supported. Signed-off-by: Ayan Kumar Halder Acked-by: Stefano Stabellini --- Changes from - v1 - 1. Extracted from "[XEN v1 8/9] xen/arm: Other adaptations required to support 32bit paddr". v2 - 1. Reordered this patch so that it appears after CONFIG_ARM_PA_32 is introduced (in 6/9). v3 - 1. Updated the commit message. 2. Added Ack. xen/arch/arm/guest_walk.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/xen/arch/arm/guest_walk.c b/xen/arch/arm/guest_walk.c index 43d3215304..c80a0ce55b 100644 --- a/xen/arch/arm/guest_walk.c +++ b/xen/arch/arm/guest_walk.c @@ -154,8 +154,10 @@ static bool guest_walk_sd(const struct vcpu *v, mask = (1ULL << L1DESC_SUPERSECTION_SHIFT) - 1; *ipa = gva & mask; *ipa |= (paddr_t)(pte.supersec.base) << L1DESC_SUPERSECTION_SHIFT; +#ifndef CONFIG_PHYS_ADDR_T_32 *ipa |= (paddr_t)(pte.supersec.extbase1) << L1DESC_SUPERSECTION_EXT_BASE1_SHIFT; *ipa |= (paddr_t)(pte.supersec.extbase2) << L1DESC_SUPERSECTION_EXT_BASE2_SHIFT; +#endif /* CONFIG_PHYS_ADDR_T_32 */ } /* Set permissions so that the caller can check the flags by herself. */