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pr=C From: Ayan Kumar Halder To: CC: , , , , , , , , , , Ayan Kumar Halder Subject: [XEN v5 10/10] xen/arm: p2m: Enable support for 32bit IPA for ARM_32 Date: Thu, 13 Apr 2023 18:37:35 +0100 Message-ID: <20230413173735.48387-11-ayan.kumar.halder@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230413173735.48387-1-ayan.kumar.halder@amd.com> References: <20230413173735.48387-1-ayan.kumar.halder@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM6NAM11FT089:EE_|SA1PR12MB5613:EE_ X-MS-Office365-Filtering-Correlation-Id: 963d6794-6a95-4b08-355b-08db3c45edca X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 5ER1z/29ZTOY8UO9h2tgQxGQDoiWQW9PGvVYq5nWExc9gg6pMYgtFW7w1Q5Ra4s+Zi41VAXLs7aRnptqUlgsuKmh5pda5q9gx3uzWw8u0IIxQPbPSlMZrNir88wnNKGTFKl+76f11tgldfVRHelY1X5BNWdaSYPitS/sWeMVP+78mey98PP6pPO62ntHqctcSdfExR6t5p2zK0iQljtupIug3ZzpzNs/QGosKzGwI5AQVROFACm4D0QyvJjn0/D/OQdcMLFwJGDIR/f2BlNt0UY3OZmtn4TNHGwn4+Da6024oqd5dTmXdiSvqho4bZPdpyDSN2G04gwC0Ky400imP0qILQod5l+sTSJns66pQFWmRn7Osb0iv4VMeuHiojBYO06dsEBAyzNbCWdcjQX3Dgz+VPrRK5WEU8JID+/gofpTFkFkA+W+z70Kun4GZb5Oy4dlJVidD6Y8ZM85QhBvIUlPLlh1QXAOLp7evGkjWFJimxaN2UFmn7G0To1hPgjiM0P4R2hjrh+Gl7dQGlMAkWZUgcdiE7pPjsSPbKxbAND6ivh+o0iNJUyQVF0aOJK9YPL7dn8HUgmg0mRqkV6vDY8XQ3VauxGDZfZ+1239M4qJUL32SqiHmo4TFC7jb34xLvBReFU94kwKtTDVnZK58h1n7SGSrqt8TZ7luwAmZ/znEzcvx5/ZMPdzI/ZTXNhwBmh4E50N7rqW6SrJdO/siEKKs1SnnKFzgItXPe4WYHc= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB03.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230028)(4636009)(136003)(39860400002)(396003)(376002)(346002)(451199021)(40470700004)(36840700001)(46966006)(103116003)(82310400005)(40460700003)(36756003)(40480700001)(478600001)(36860700001)(4326008)(6916009)(8676002)(70586007)(70206006)(41300700001)(316002)(54906003)(2616005)(47076005)(83380400001)(426003)(336012)(6666004)(186003)(1076003)(26005)(86362001)(5660300002)(7416002)(356005)(82740400003)(8936002)(81166007)(2906002)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Apr 2023 17:38:44.2105 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 963d6794-6a95-4b08-355b-08db3c45edca X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT089.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA1PR12MB5613 Refer ARM DDI 0406C.d ID040418, B3-1345, "A stage 2 translation with an input address range of 31-34 bits can start the translation either: - With a first-level lookup, accessing a first-level translation table with 2-16 entries. - With a second-level lookup, accessing a set of concatenated second-level translation tables" Thus, for 32 bit IPA, there will be no concatenated root level tables. So, the root-order is 0. Also, Refer ARM DDI 0406C.d ID040418, B3-1348 "Determining the required first lookup level for stage 2 translations For a stage 2 translation, the output address range from the stage 1 translations determines the required input address range for the stage 2 translation. The permitted values of VTCR.SL0 are: 0b00 Stage 2 translation lookup must start at the second level. 0b01 Stage 2 translation lookup must start at the first level. VTCR.T0SZ must indicate the required input address range. The size of the input address region is 2^(32-T0SZ) bytes." Thus VTCR.SL0 = 1 (maximum value) and VTCR.T0SZ = 0 when the size of input address region is 2^32 bytes. Signed-off-by: Ayan Kumar Halder --- Changes from - v1 - New patch. v2 - 1. Added Ack. v3 - 1. Dropped Ack. 2. Rebased the patch based on the previous change. v4 - 1. t0sz is 0 for 32-bit IPA on Arm32. 2. Updated the commit message to explain t0sz, sl0 and root_order. xen/arch/arm/p2m.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/xen/arch/arm/p2m.c b/xen/arch/arm/p2m.c index 4583658f92..746b6553e5 100644 --- a/xen/arch/arm/p2m.c +++ b/xen/arch/arm/p2m.c @@ -2283,7 +2283,8 @@ void __init setup_virt_paging(void) [6] = { 52, 12/*12*/, 4, 2 }, [7] = { 0 } /* Invalid */ #else - [1] = { 0 } /* Invalid */ + [1] = { 32, 0/*0*/, 0, 1 }, + [2] = { 0 } /* Invalid */ #endif };