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pr=C From: Ayan Kumar Halder To: CC: , , , , , , , , , , Ayan Kumar Halder Subject: [XEN v6 12/12] xen/arm: p2m: Enable support for 32bit IPA for ARM_32 Date: Fri, 28 Apr 2023 18:55:43 +0100 Message-ID: <20230428175543.11902-13-ayan.kumar.halder@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230428175543.11902-1-ayan.kumar.halder@amd.com> References: <20230428175543.11902-1-ayan.kumar.halder@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL02EPF000145BA:EE_|DM4PR12MB5119:EE_ X-MS-Office365-Filtering-Correlation-Id: 3971b29a-7fbf-41fd-fdde-08db4812536d X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: DWLYNZ4mdaXyrDy44o5pO4nuzXBOGZEtLPYFscggbmlZtxJ9wyw+eJqOcOtdlufEtVTrZG4ykzuiEZwQCU+tnGq0ht18PIR4IGQdjspt6y+xtH72sU/DMRANHXEzN59hb35ht3gB2BZj5q1GtxgeT3jIBxIQ5+g4JwgANn6YnhlyxJdtXzWAemfIXshC4MnqYlFps3hYLqWi7Uo5mEOs8kFB4114kWDqJ3nVgUT5F7xacBGtAMzcgE9WzG8CtOVZFHCuN8PdD+f2gvEfbRnx6a8174W4UVzrPbzzqMQOfVtMKr3K9ONqoopTYRsBYBhuBJiNsUD3Ztb+pqwod0jwFOB8d3mImBNgmC7ngwckDzOjm9heyGRiiiHHbEmTKJN2G5xsfFnRakSHxvHCKbke+F60pNonUxHA87yQ120t4ORBaXw6c+LBStNdQecWQmBiNfQWKBD3OwsPwzeUcfv10t3KNBGLGPahLn4YMYoGiy6Htv1T3J/ehIGWtI1gxty3pcNE98GdXqzQMqo+pgUXPdH/2npdtSDCPqZLJ/ZLx8Zu7zICAhMc9O6T90MeIiEt48VWC4gy1iT0s4C5h41JrsZppJFd3M29OY8BB7iFPBeT+4MxvrP4CaQ2JgLcaMdi6gPZVcUy5QZnPzeyVe95zD6AhHFX9p7OZkThXocpO5BgBlZalU77cdVdzxUul8NsIgDMsODZiyLAoOqbsmCW5r8HNpSkpwX7zZe9XUeSe3A= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB03.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230028)(4636009)(39860400002)(346002)(136003)(376002)(396003)(451199021)(40470700004)(36840700001)(46966006)(186003)(26005)(1076003)(41300700001)(81166007)(356005)(6666004)(426003)(83380400001)(47076005)(336012)(36860700001)(2616005)(478600001)(54906003)(40460700003)(82310400005)(7416002)(82740400003)(70206006)(70586007)(4326008)(6916009)(40480700001)(316002)(5660300002)(36756003)(2906002)(103116003)(86362001)(8936002)(8676002)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 28 Apr 2023 17:59:34.8916 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 3971b29a-7fbf-41fd-fdde-08db4812536d X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF000145BA.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB5119 Refer ARM DDI 0406C.d ID040418, B3-1345, "A stage 2 translation with an input address range of 31-34 bits can start the translation either: - With a first-level lookup, accessing a first-level translation table with 2-16 entries. - With a second-level lookup, accessing a set of concatenated second-level translation tables" Thus, for 32 bit IPA, there will be no concatenated root level tables. So, the root-order is 0. Also, Refer ARM DDI 0406C.d ID040418, B3-1348 "Determining the required first lookup level for stage 2 translations For a stage 2 translation, the output address range from the stage 1 translations determines the required input address range for the stage 2 translation. The permitted values of VTCR.SL0 are: 0b00 Stage 2 translation lookup must start at the second level. 0b01 Stage 2 translation lookup must start at the first level. VTCR.T0SZ must indicate the required input address range. The size of the input address region is 2^(32-T0SZ) bytes." Thus VTCR.SL0 = 1 (maximum value) and VTCR.T0SZ = 0 when the size of input address region is 2^32 bytes. Signed-off-by: Ayan Kumar Halder --- Changes from - v1 - New patch. v2 - 1. Added Ack. v3 - 1. Dropped Ack. 2. Rebased the patch based on the previous change. v4 - 1. t0sz is 0 for 32-bit IPA on Arm32. 2. Updated the commit message to explain t0sz, sl0 and root_order. v5 - 1. Rebased on top of the changes in the previous patch. xen/arch/arm/p2m.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/xen/arch/arm/p2m.c b/xen/arch/arm/p2m.c index 1fe3cccf46..6e13772cbc 100644 --- a/xen/arch/arm/p2m.c +++ b/xen/arch/arm/p2m.c @@ -2265,7 +2265,7 @@ void __init setup_virt_paging(void) [6] = { 52, 12/*12*/, 4, 2 }, [7] = { 0 } /* Invalid */ #else - [0] = { 0 }, /* Invalid */ + [0] = { 32, 0/*0*/, 0, 1 }, [1] = { 0 }, /* Invalid */ [3] = { 0 } /* Invalid */ #endif