Message ID | 20230518143920.43186-12-ayan.kumar.halder@amd.com (mailing list archive) |
---|---|
State | Superseded |
Headers | show
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pr=C From: Ayan Kumar Halder <ayan.kumar.halder@amd.com> To: <xen-devel@lists.xenproject.org> CC: <sstabellini@kernel.org>, <stefano.stabellini@amd.com>, <julien@xen.org>, <Volodymyr_Babchuk@epam.com>, <bertrand.marquis@arm.com>, <andrew.cooper3@citrix.com>, <george.dunlap@citrix.com>, <jbeulich@suse.com>, <wl@xen.org>, <rahul.singh@arm.com>, <michal.orzel@amd.com>, "Ayan Kumar Halder" <ayan.kumar.halder@amd.com> Subject: [XEN v7 11/11] xen/arm: p2m: Enable support for 32bit IPA for ARM_32 Date: Thu, 18 May 2023 15:39:20 +0100 Message-ID: <20230518143920.43186-12-ayan.kumar.halder@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230518143920.43186-1-ayan.kumar.halder@amd.com> References: <20230518143920.43186-1-ayan.kumar.halder@amd.com> MIME-Version: 1.0 Content-Type: text/plain X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT065:EE_|PH8PR12MB6961:EE_ X-MS-Office365-Filtering-Correlation-Id: 7efc5c60-cf6f-4e54-b064-08db57ae1b6b X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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Add support for 32-bit physical address
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expand
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diff --git a/xen/arch/arm/p2m.c b/xen/arch/arm/p2m.c index 755cb86c5b..08b209e7c9 100644 --- a/xen/arch/arm/p2m.c +++ b/xen/arch/arm/p2m.c @@ -2265,6 +2265,7 @@ void __init setup_virt_paging(void) [6] = { 52, 12/*12*/, 4, 2 }, [7] = { 0 } /* Invalid */ #else + { 32, 0/*0*/, 0, 1 }, { 40, 24/*24*/, 1, 1 }, { 0 }, /* Invalid */ #endif
Refer ARM DDI 0406C.d ID040418, B3-1345, "A stage 2 translation with an input address range of 31-34 bits can start the translation either: - With a first-level lookup, accessing a first-level translation table with 2-16 entries. - With a second-level lookup, accessing a set of concatenated second-level translation tables" Thus, for 32 bit IPA, there will be no concatenated root level tables. So, the root-order is 0. Also, Refer ARM DDI 0406C.d ID040418, B3-1348 "Determining the required first lookup level for stage 2 translations For a stage 2 translation, the output address range from the stage 1 translations determines the required input address range for the stage 2 translation. The permitted values of VTCR.SL0 are: 0b00 Stage 2 translation lookup must start at the second level. 0b01 Stage 2 translation lookup must start at the first level. VTCR.T0SZ must indicate the required input address range. The size of the input address region is 2^(32-T0SZ) bytes." Thus VTCR.SL0 = 1 (maximum value) and VTCR.T0SZ = 0 when the size of input address region is 2^32 bytes. Signed-off-by: Ayan Kumar Halder <ayan.kumar.halder@amd.com> --- Changes from - v1 - New patch. v2 - 1. Added Ack. v3 - 1. Dropped Ack. 2. Rebased the patch based on the previous change. v4 - 1. t0sz is 0 for 32-bit IPA on Arm32. 2. Updated the commit message to explain t0sz, sl0 and root_order. v5 - 1. Rebased on top of the changes in the previous patch. v6 - 1. Removed the index for ARM_32. xen/arch/arm/p2m.c | 1 + 1 file changed, 1 insertion(+)