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pr=C From: Ayan Kumar Halder To: CC: , , , , , , , , , , Ayan Kumar Halder Subject: [XEN v8 3/5] xen/arm: guest_walk: LPAE specific bits should be enclosed within "ifndef CONFIG_PHYS_ADDR_T_32" Date: Fri, 2 Jun 2023 13:07:52 +0100 Message-ID: <20230602120754.23817-4-ayan.kumar.halder@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230602120754.23817-1-ayan.kumar.halder@amd.com> References: <20230602120754.23817-1-ayan.kumar.halder@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT013:EE_|CH3PR12MB7665:EE_ X-MS-Office365-Filtering-Correlation-Id: 7664218c-6fcd-4154-c92d-08db63623199 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: gR/sFpaMzdy2d/TlzBhEiMTbs7whgyxw4fKEGbaDjsx61T2ba58+JSss7iCaaYn3nNxcm8NrLmtCvVG40g7HqRGHncTV3eTlARuTD7AFa8Y/pKwBhzoDy2Bgknfki5K6tUz/QIVt6zeRjhThOkoLFrysYSviYJKx8wMnpSN3WSswprv4tYCjWr+HS9kvZgkmgVRmqpvNsLiBrY2QA+S6zqX4vRq0L+BhZ7PljlyObwXGpTqNGixVlFVAYoNbSAVG1k8VRWJNURouk2MDodHEjYoIPJDfxzMjiHRieoA5KsNaliMSNduqFp5dmywMf+WHyv+a6bRaju+nfhJ0Rp3tK+btPueh3dXRoy0rJh5QP+drcsVNceY9fe2+e/MaijMeL2NZZ+hF5COHQ+6ABYsDrb6ni1goOZGydM9xDBNGp0mXgVl3Q1mELRSrqyTfJtT87vECe7ym0lh6+8n9G4b9E4GNgpZn+MGbMRLilRvXtpHsdanA9b6kWAf+J1USnceE0EIZ3Kn+71RnaL1/aR5HjpQvRcI6VN1dXO5NO5K+db782HFBqOoXSv3cGS/AIh8EIbZhevyTNnLc+i1HHDch36EOzIn1mFtPTtdMT6YxDiD/On3UkOVCE8OznD2ucdFEcneESzfiDPrTjHE2kDvOJB9GZPqy696Z0nRmpW8xoTj3ARopwu9/+47YaOZtngJvL3ClfaQ0OLncOY9SQzT0OcB6JgsLgQj01aNqJeEwUgaNqq3N00Wmt0gIqQrySpGwtVzAofW6yANoYFy7AnCq7g== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB03.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230028)(4636009)(136003)(376002)(396003)(39860400002)(346002)(451199021)(36840700001)(40470700004)(46966006)(40460700003)(426003)(336012)(83380400001)(2616005)(47076005)(186003)(2906002)(36860700001)(4326008)(6916009)(70586007)(316002)(6666004)(478600001)(8936002)(54906003)(70206006)(5660300002)(1076003)(26005)(8676002)(7416002)(40480700001)(41300700001)(356005)(82740400003)(36756003)(103116003)(82310400005)(86362001)(81166007)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 02 Jun 2023 12:09:19.2695 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 7664218c-6fcd-4154-c92d-08db63623199 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT013.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH3PR12MB7665 As the previous patch introduces CONFIG_PHYS_ADDR_T_32 to support 32 bit physical addresses, the code specific to "Large Physical Address Extension" (ie LPAE) should be enclosed within "ifndef CONFIG_PHYS_ADDR_T_32". Refer xen/arch/arm/include/asm/short-desc.h, "short_desc_l1_supersec_t" unsigned int extbase1:4; /* Extended base address, PA[35:32] */ unsigned int extbase2:4; /* Extended base address, PA[39:36] */ Thus, extbase1 and extbase2 are not valid when 32 bit physical addresses are supported. Signed-off-by: Ayan Kumar Halder Acked-by: Stefano Stabellini --- Changes from - v1 - 1. Extracted from "[XEN v1 8/9] xen/arm: Other adaptations required to support 32bit paddr". v2 - 1. Reordered this patch so that it appears after CONFIG_ARM_PA_32 is introduced (in 6/9). v3 - 1. Updated the commit message. 2. Added Ack. v4 - 1. No changes. v5 - 1. No changes. v6 - 1. No changes. v7 - 1. No changes. xen/arch/arm/guest_walk.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/xen/arch/arm/guest_walk.c b/xen/arch/arm/guest_walk.c index 43d3215304..c80a0ce55b 100644 --- a/xen/arch/arm/guest_walk.c +++ b/xen/arch/arm/guest_walk.c @@ -154,8 +154,10 @@ static bool guest_walk_sd(const struct vcpu *v, mask = (1ULL << L1DESC_SUPERSECTION_SHIFT) - 1; *ipa = gva & mask; *ipa |= (paddr_t)(pte.supersec.base) << L1DESC_SUPERSECTION_SHIFT; +#ifndef CONFIG_PHYS_ADDR_T_32 *ipa |= (paddr_t)(pte.supersec.extbase1) << L1DESC_SUPERSECTION_EXT_BASE1_SHIFT; *ipa |= (paddr_t)(pte.supersec.extbase2) << L1DESC_SUPERSECTION_EXT_BASE2_SHIFT; +#endif /* CONFIG_PHYS_ADDR_T_32 */ } /* Set permissions so that the caller can check the flags by herself. */