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pr=C From: Ayan Kumar Halder To: CC: , , , , , , , , , , Ayan Kumar Halder Subject: [XEN v8 4/5] xen/arm: Restrict zeroeth_table_offset for ARM_64 Date: Fri, 2 Jun 2023 13:07:53 +0100 Message-ID: <20230602120754.23817-5-ayan.kumar.halder@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230602120754.23817-1-ayan.kumar.halder@amd.com> References: <20230602120754.23817-1-ayan.kumar.halder@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1NAM11FT048:EE_|DM6PR12MB4530:EE_ X-MS-Office365-Filtering-Correlation-Id: 3f2c90ab-c47d-42a7-0e7f-08db636239b3 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: NHHBN9100Obhp8+lRd0lDby/XDtUD58YAhaQFeYAti+/qJH4bz3OJTd4TRmgsL7G7c256PlcYxBn+cPInVdK4kqjnVmjwmOY12p5MmCmABCt0mBK3YZZdky1rC6XmLj+5WH53cu2GFxvJqbx0VIvT1TkKHpJdDdN+DU4Q6LoAE+7yksoHWTfMwZn/0gnOKt9DIvMtP6APqqJt1ByvADMOmVOSVpx5GezOwE/8xk+KKjHLOYV4Ec3iCMqx0EZAGml4GC8HyiASRTlwj2bHreLqYDhYI2IM/ddS4/oMcBiMKDyfCFInW5lrAznyH7uS9fbSGy2ZQjqnid3LyeqdZWbfluTiDp7VG8FSgEF/d30c7hGyGS9zK1GCWRPs46eHN4o9bqtg6atnyHoFC993nPzbBLXIQbnYfV3wbXTrSdkgbcOlCXJtCcS1CvKnVftBeKst2lhkgIH7OR8RmY9KRRrlGHLm9eIOqGtEtlCYdQvqHfoF4JY5WoqP14KRGtFtNJSSrApGbZG8UXf5YNO4S7bppmGrT80MclkdNdzJizST02RKJtrkkaWrrBziOyDzcEPCiYVgkPdFoRjstPro83l98bITHM58682iXCmttExucLk47Txc+W7kzPpaxkuTMcC20e3t/V0wRY70+C9suFyLzLij34a5bWKIOdapMmfDHqjFQf/bSLAxKVpXmUK6kQWZGzqnIfV0gNfbVkY4dP0Ew9BFLyMh/bkK6e9CPOOOcar7P+TG6oAeytw6aMirmQ7I/ANHUkqoMNqnPxkZq0xFw== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230028)(4636009)(376002)(136003)(39860400002)(346002)(396003)(451199021)(46966006)(40470700004)(36840700001)(82310400005)(4326008)(81166007)(356005)(47076005)(103116003)(26005)(1076003)(40460700003)(7416002)(2906002)(86362001)(5660300002)(8936002)(8676002)(186003)(6666004)(36756003)(54906003)(426003)(2616005)(336012)(316002)(82740400003)(83380400001)(41300700001)(40480700001)(36860700001)(478600001)(70586007)(70206006)(6916009)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 02 Jun 2023 12:09:32.7163 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 3f2c90ab-c47d-42a7-0e7f-08db636239b3 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT048.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB4530 When 32 bit physical addresses are used (ie PHYS_ADDR_T_32=y), "va >> ZEROETH_SHIFT" causes an overflow. Also, there is no zeroeth level page table on Arm32. Also took the opportunity to clean up dump_pt_walk(). One could use DECLARE_OFFSETS() macro instead of declaring an array of page table offsets. Signed-off-by: Ayan Kumar Halder Reviewed-by: Michal Orzel Acked-by: Julien Grall --- Changes from - v1 - Removed the duplicate declaration for DECLARE_OFFSETS. v2 - 1. Reworded the commit message. 2. Use CONFIG_ARM_PA_32 to restrict zeroeth_table_offset. v3 - 1. Added R-b and Ack. v4 - 1. Removed R-b and Ack as we use CONFIG_PHYS_ADDR_T_32 instead of CONFIG_ARM_PA_BITS_32. This is to be in parity with our earlier patches where we use CONFIG_PHYS_ADDR_T_32 to denote 32-bit physical addr support. v5 - 1. Added R-b and Ack. v6 - 1. No changes. v7 - 1. No changes. xen/arch/arm/include/asm/lpae.h | 4 ++++ xen/arch/arm/mm.c | 7 +------ 2 files changed, 5 insertions(+), 6 deletions(-) diff --git a/xen/arch/arm/include/asm/lpae.h b/xen/arch/arm/include/asm/lpae.h index 3fdd5d0de2..7d2f6fd1bd 100644 --- a/xen/arch/arm/include/asm/lpae.h +++ b/xen/arch/arm/include/asm/lpae.h @@ -259,7 +259,11 @@ lpae_t mfn_to_xen_entry(mfn_t mfn, unsigned int attr); #define first_table_offset(va) TABLE_OFFSET(first_linear_offset(va)) #define second_table_offset(va) TABLE_OFFSET(second_linear_offset(va)) #define third_table_offset(va) TABLE_OFFSET(third_linear_offset(va)) +#ifdef CONFIG_PHYS_ADDR_T_32 +#define zeroeth_table_offset(va) 0 +#else #define zeroeth_table_offset(va) TABLE_OFFSET(zeroeth_linear_offset(va)) +#endif /* * Macros to define page-tables: diff --git a/xen/arch/arm/mm.c b/xen/arch/arm/mm.c index 5ef5fd8c49..e460249736 100644 --- a/xen/arch/arm/mm.c +++ b/xen/arch/arm/mm.c @@ -233,12 +233,7 @@ void dump_pt_walk(paddr_t ttbr, paddr_t addr, { static const char *level_strs[4] = { "0TH", "1ST", "2ND", "3RD" }; const mfn_t root_mfn = maddr_to_mfn(ttbr); - const unsigned int offsets[4] = { - zeroeth_table_offset(addr), - first_table_offset(addr), - second_table_offset(addr), - third_table_offset(addr) - }; + DECLARE_OFFSETS(offsets, addr); lpae_t pte, *mapping; unsigned int level, root_table;