@@ -847,17 +847,21 @@ int __init early_microcode_init(unsigned long *module_map,
{
const struct cpuinfo_x86 *c = &boot_cpu_data;
int rc = 0;
+ bool can_load = false;
switch ( c->x86_vendor )
{
case X86_VENDOR_AMD:
if ( c->x86 >= 0x10 )
+ {
ucode_ops = amd_ucode_ops;
+ can_load = true;
+ }
break;
case X86_VENDOR_INTEL:
- if ( c->x86 >= 6 )
- ucode_ops = intel_ucode_ops;
+ ucode_ops = intel_ucode_ops;
+ can_load = intel_can_load_microcode();
break;
}
@@ -874,7 +878,7 @@ int __init early_microcode_init(unsigned long *module_map,
* mean that they will not accept microcode updates. We take the hint
* and ignore the microcode interface in that case.
*/
- if ( this_cpu(cpu_sig).rev == ~0 ) {
+ if ( this_cpu(cpu_sig).rev == ~0 || !can_load ) {
printk(XENLOG_WARNING "Microcode loading disabled\n");
ucode_ops.apply_microcode = NULL;
return -ENODEV;
@@ -385,6 +385,19 @@ static struct microcode_patch *cf_check cpu_request_microcode(
return patch;
}
+bool __init intel_can_load_microcode(void)
+{
+ uint64_t mcu_ctrl;
+
+ if ( !cpu_has_mcu_ctrl )
+ return true;
+
+ rdmsrl(MSR_MCU_CONTROL, mcu_ctrl);
+
+ /* If DIS_MCU_LOAD is set applying microcode updates won't work */
+ return !(mcu_ctrl & MCU_CONTROL_DIS_MCU_LOAD);
+}
+
const struct microcode_ops __initconst_cf_clobber intel_ucode_ops = {
.cpu_request_microcode = cpu_request_microcode,
.collect_cpu_info = collect_cpu_info,
@@ -60,6 +60,13 @@ struct microcode_ops {
const struct microcode_patch *new, const struct microcode_patch *old);
};
+/**
+ * Checks whether we can perform microcode updates on this Intel system
+ *
+ * @return True iff the microcode update facilities are enabled
+ */
+bool __init intel_can_load_microcode(void);
+
extern const struct microcode_ops amd_ucode_ops, intel_ucode_ops;
#endif /* ASM_X86_MICROCODE_PRIVATE_H */
@@ -192,6 +192,7 @@ static inline bool boot_cpu_has(unsigned int feat)
#define cpu_has_if_pschange_mc_no boot_cpu_has(X86_FEATURE_IF_PSCHANGE_MC_NO)
#define cpu_has_tsx_ctrl boot_cpu_has(X86_FEATURE_TSX_CTRL)
#define cpu_has_taa_no boot_cpu_has(X86_FEATURE_TAA_NO)
+#define cpu_has_mcu_ctrl boot_cpu_has(X86_FEATURE_MCU_CTRL)
#define cpu_has_fb_clear boot_cpu_has(X86_FEATURE_FB_CLEAR)
#define cpu_has_rrsba boot_cpu_has(X86_FEATURE_RRSBA)
@@ -165,6 +165,11 @@
#define PASID_PASID_MASK 0x000fffff
#define PASID_VALID (_AC(1, ULL) << 31)
+#define MSR_MCU_CONTROL 0x00001406
+#define MCU_CONTROL_LOCK (_AC(1, ULL) << 0)
+#define MCU_CONTROL_DIS_MCU_LOAD (_AC(1, ULL) << 1)
+#define MCU_CONTROL_EN_SMM_BYPASS (_AC(1, ULL) << 2)
+
#define MSR_UARCH_MISC_CTRL 0x00001b01
#define UARCH_CTRL_DOITM (_AC(1, ULL) << 0)
If IA32_MSR_MCU_CONTROL exists then it's possible a CPU may be unable to perform microcode updates. This is controlled through the DIS_MCU_LOAD bit and is intended for baremetal clouds where the owner may not trust the tenant to choose the microcode version in use. If we notice that bit being set then simply disable the "apply_microcode" handler so we can't even try to perform update (as it's known to be silently dropped). While at it, remove the Intel family check, as microcode loading is supported on every Intel 64 CPU. Signed-off-by: Alejandro Vallejo <alejandro.vallejo@cloud.com> --- v4: * Moved the Intel family-check removal here. Previously integrated in other patches * Moved DIS_MCU_LOAD logic into a vendor-specific intel_can_load_microcode() function. --- xen/arch/x86/cpu/microcode/core.c | 10 +++++++--- xen/arch/x86/cpu/microcode/intel.c | 13 +++++++++++++ xen/arch/x86/cpu/microcode/private.h | 7 +++++++ xen/arch/x86/include/asm/cpufeature.h | 1 + xen/arch/x86/include/asm/msr-index.h | 5 +++++ 5 files changed, 33 insertions(+), 3 deletions(-)