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pr=C From: Stewart Hildebrand To: CC: Stewart Hildebrand , =?utf-8?q?Roger_Pau_Mon?= =?utf-8?q?n=C3=A9?= Subject: [PATCH v1 3/3] xen/vpci: header: filter PCI capabilities Date: Thu, 10 Aug 2023 15:12:59 -0400 Message-ID: <20230810191312.644235-4-stewart.hildebrand@amd.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230810191312.644235-1-stewart.hildebrand@amd.com> References: <20230810191312.644235-1-stewart.hildebrand@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1PEPF000042AB:EE_|CH3PR12MB9021:EE_ X-MS-Office365-Filtering-Correlation-Id: 6e943005-87f0-423d-d03a-08db99d5f9cc X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: EwROm0Lbzsr56+VaUvR7rQPESxbMiOqRULxVl7GoRBE2pD61dGhhYSAeUNKWjN7WH7qDndzcU0Sm/RakmAYVW4ox3rndqLs39STuYsxwT4BpIAkaHPqNaVY8wjEgS7RK/vWzEBBuETb/HZAVMayeE/M0VsnC/GX7+j/xXf0m6BxkGHWb+iLgOzdBDx2uFSzBevvA6PbMuBDteOkrzecANCs4z7eOdWgvtjSfPcHFds9yRK59oRjga8EowIwlWU/Gz+HU/IEtwAitjuWLXaTuh4t1vsrZndSQeYRRKXmqSE9LmHOgMQkZ8on/b6xLX5kHEiIvgIAdRm0ic6FCvDHlOz2005D0Lyx/exP0qnlSQI7LhBUPYlkAwuWpLAvmSK/C/TjbqlsXgYpLK0/JgO6/oA18C3rbzJtkZfE+NG9n1bcnP8jwnWUODJfvqwplaCd2cBXaJHFBvAppW/9XsU2Y/ACD4q8r5pyRlaOcAOSWGxvfuiih/141XXsTvUemFM/ZLpaFpcOHM+yoXWLPKF89wJ5INJtyfJ5IVhYPplMdvPrkiUAa+YERi/wces660K4GYNy9VB5Pd0aL6KR6GBtt0biqiTQLtm6HFQ1ZlQnRJzpwMBireaV+SZbj6DObeDguBSG9RZisHy2iMbbgmzUW9PyLdS+qf/FqFsIfvee+TSqh3j2l34gmDTM17Gy16jYpClLsxHfswcvmxShyvX1ud0H2Kf+dxv/zR5e0lLZvCmOesSbb7X3XvJSVv1AFluHpovcmwfajrMMTX/33XJQXow== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB03.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230028)(4636009)(376002)(39860400002)(346002)(136003)(396003)(1800799006)(451199021)(82310400008)(186006)(36840700001)(40470700004)(46966006)(8676002)(8936002)(1076003)(26005)(41300700001)(40460700003)(36860700001)(36756003)(47076005)(426003)(2906002)(356005)(2616005)(81166007)(86362001)(82740400003)(44832011)(336012)(6916009)(70206006)(70586007)(4326008)(54906003)(478600001)(5660300002)(40480700001)(6666004)(316002)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 Aug 2023 19:14:09.9684 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 6e943005-87f0-423d-d03a-08db99d5f9cc X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1PEPF000042AB.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH3PR12MB9021 Xen vPCI only supports virtualizing the MSI and MSI-X capabilities, so all other PCI capabilities should be hidden from a domU for now. We parse the physical PCI capabilities linked list and add vPCI register handlers for the next elements, inserting our own next value, thus presenting a modified linked list to the domU. Signed-off-by: Stewart Hildebrand --- If there are no capabilities to be exposed to the guest, a future status register handler likely would want to mask the PCI_STATUS_CAP_LIST bit. I'm thinking we could track this in struct vpci_header as follows: vpci.h: struct vpci_header { ... + bool mask_cap_list : 1; } header; header.c:init_bars(): rc = vpci_add_register(pdev->vpci, vpci_read_val, NULL, PCI_CAPABILITY_LIST, 1, (void *)(uintptr_t)next); if ( rc ) return rc; + if ( !next ) + header->mask_cap_list = true; + for ( ttl = 48; ttl > 0; ttl-- ) { uint8_t pos; --- xen/drivers/vpci/header.c | 78 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 78 insertions(+) diff --git a/xen/drivers/vpci/header.c b/xen/drivers/vpci/header.c index 60f7049e3498..cb1304fa1eed 100644 --- a/xen/drivers/vpci/header.c +++ b/xen/drivers/vpci/header.c @@ -513,6 +513,36 @@ static void cf_check rom_write( rom->addr = val & PCI_ROM_ADDRESS_MASK; } +static uint8_t vpci_find_next_cap(pci_sbdf_t sbdf, uint8_t pos) +{ + uint8_t id; + int ttl; + + if ( pos < 0x40 ) + pos = pci_conf_read8(sbdf, PCI_CAPABILITY_LIST); + else + pos = pci_conf_read8(sbdf, pos + PCI_CAP_LIST_NEXT); + + for ( ttl = 48; ttl > 0; ttl-- ) + { + if ( pos < 0x40 ) + break; + + pos &= ~3; + id = pci_conf_read8(sbdf, pos + PCI_CAP_LIST_ID); + + if ( id == 0xff ) + break; + + if ( id == PCI_CAP_ID_MSI || + id == PCI_CAP_ID_MSIX ) + return pos; + + pos = pci_conf_read8(sbdf, pos + PCI_CAP_LIST_NEXT); + } + return 0; +} + static int cf_check init_bars(struct pci_dev *pdev) { uint16_t cmd; @@ -544,6 +574,54 @@ static int cf_check init_bars(struct pci_dev *pdev) if ( rc ) return rc; + if ( !is_hardware_domain(pdev->domain) ) + { + if ( (pci_conf_read16(pdev->sbdf, PCI_STATUS) & PCI_STATUS_CAP_LIST) + == 0 ) + { + /* RAZ/WI */ + rc = vpci_add_register(pdev->vpci, vpci_read_val, NULL, + PCI_CAPABILITY_LIST, 1, NULL); + if ( rc ) + return rc; + } + else + { + /* Only expose capabilities to the guest that vPCI can handle. */ + uint8_t next, ttl; + + next = vpci_find_next_cap(pdev->sbdf, PCI_CAPABILITY_LIST); + + rc = vpci_add_register(pdev->vpci, vpci_read_val, NULL, + PCI_CAPABILITY_LIST, 1, + (void *)(uintptr_t)next); + if ( rc ) + return rc; + + for ( ttl = 48; ttl > 0; ttl-- ) + { + uint8_t pos; + + if ( !next ) + break; + + pos = next; + next = vpci_find_next_cap(pdev->sbdf, pos); + + rc = vpci_add_register(pdev->vpci, vpci_hw_read8, NULL, + pos + PCI_CAP_LIST_ID, 1, NULL); + if ( rc ) + return rc; + + rc = vpci_add_register(pdev->vpci, vpci_read_val, NULL, + pos + PCI_CAP_LIST_NEXT, 1, + (void *)(uintptr_t)next); + if ( rc ) + return rc; + } + } + } + if ( pdev->ignore_bars ) return 0;