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pr=C From: Stewart Hildebrand To: CC: Stewart Hildebrand , =?utf-8?q?Roger_Pau_Mon?= =?utf-8?q?n=C3=A9?= Subject: [PATCH v4 4/6] xen/vpci: header: status register handler Date: Mon, 28 Aug 2023 13:56:52 -0400 Message-ID: <20230828175858.30780-5-stewart.hildebrand@amd.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20230828175858.30780-1-stewart.hildebrand@amd.com> References: <20230828175858.30780-1-stewart.hildebrand@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000EE3B:EE_|SJ2PR12MB8035:EE_ X-MS-Office365-Filtering-Correlation-Id: 98d8a99c-88b4-4537-af11-08dba7f0e1f6 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: /NrZaw/dF2KnJ1SojurgEW8oPSC3Jv/yQT107KcDCJpGRL4w5kFzNhIHpuVM/JOWNivAbhvUFHGslHVLXnmQ7ubJ7y048ywaSZQSYB0mOhPrMqm54c8JgrkZJOTwXeI/LEDywmtyXhs5ZJ1NO+MYAFqXoBLcb8pViuDtvmwmtULddavbz5pX3G5LiWkZH1UMDh1aeGnK0vBfX/qIINXqBfUuTnQWbi6nkDbXNkqgszmptAEX/l4WRf6GChFhcls9UyzgTYUHnzWy3uVz7Q613zNbTdmnQxP6AhymuleivcAiZo5pjCH7ULrmtDCfTEzU01+HP4cEofjPPXnOMYcxgp5wt2vUxK81OJ/3/r8MDJr8WwrzMzoVmhKJfnbABj/fHYsr+iWdh+V8L6oomJvIZujbub4GDt52k/gw9KRItlP+0aKRTCTQ8I2ZWjVcQuWmGgCg9C5Grw0l1hGmx6PRPt4jEbdcXEZCrW2PkrEdy8HhNbH7kVhFQ0y5434B5iTV0FU4/K3a9EujwGm9gRHrxlWve86x0C+wKwP7MZ5FKfCL+ga1JN5UwMDv4Kzl0JMWbWfX/5m2PyTxchvdV4rBRCAAh+zcElF/2QtEH4m+vUrKOB1Bo7Zrva5Ufi3hDugu/hXgBPeCTiMnzqjM17Os00PEiceHZ+cTxGtViqB8CYugXh2HtJEpqDEDyRCAjBMwqb+HGF2Yh2/wgMFpl5RpbtU2R/v47c3kgzGk0W9pqoJ6eRwBa46vrEo8CzBVgH4wOyye3UeZgWq5PjMaJ8vilNjHMjHoQTnOApWn1LmtsaA= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230031)(4636009)(396003)(376002)(39860400002)(136003)(346002)(1800799009)(82310400011)(451199024)(186009)(46966006)(40470700004)(36840700001)(478600001)(83380400001)(81166007)(356005)(82740400003)(26005)(336012)(426003)(47076005)(36860700001)(1076003)(2616005)(40480700001)(66899024)(6666004)(86362001)(2906002)(44832011)(316002)(4326008)(6916009)(70206006)(5660300002)(8676002)(70586007)(41300700001)(8936002)(54906003)(36756003)(40460700003)(36900700001)(357404004);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 28 Aug 2023 18:02:02.6993 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 98d8a99c-88b4-4537-af11-08dba7f0e1f6 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000EE3B.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ2PR12MB8035 Introduce a handler for the PCI status register, with ability to mask the capabilities bit. The status register is write-1-to-clear, so introduce handling for this type of register in vPCI. The mask_cap_list flag will be set in a follow-on patch. Signed-off-by: Stewart Hildebrand --- v3->v4: * move mask_cap_list setting to the capabilities patch * single pci_conf_read16 in status_read * align mask_cap_list bitfield in struct vpci_header * change to rw1c bit mask instead of treating whole register as rw1c * drop subsystem prefix on renamed add_register function v2->v3: * new patch --- xen/drivers/vpci/header.c | 17 +++++++++++++++++ xen/drivers/vpci/vpci.c | 36 ++++++++++++++++++++++++++++-------- xen/include/xen/vpci.h | 9 +++++++++ 3 files changed, 54 insertions(+), 8 deletions(-) diff --git a/xen/drivers/vpci/header.c b/xen/drivers/vpci/header.c index 767c1ba718d7..dc8c6a66770b 100644 --- a/xen/drivers/vpci/header.c +++ b/xen/drivers/vpci/header.c @@ -413,6 +413,18 @@ static void cf_check cmd_write( pci_conf_write16(pdev->sbdf, reg, cmd); } +static uint32_t cf_check status_read(const struct pci_dev *pdev, + unsigned int reg, void *data) +{ + struct vpci_header *header = data; + uint32_t status = pci_conf_read16(pdev->sbdf, reg); + + if ( header->mask_cap_list ) + status &= ~PCI_STATUS_CAP_LIST; + + return status; +} + static void cf_check bar_write( const struct pci_dev *pdev, unsigned int reg, uint32_t val, void *data) { @@ -544,6 +556,11 @@ static int cf_check init_bars(struct pci_dev *pdev) if ( rc ) return rc; + rc = vpci_add_rw1c_register(pdev->vpci, status_read, vpci_hw_write16, + PCI_STATUS, 2, header, 0xF900); + if ( rc ) + return rc; + if ( pdev->ignore_bars ) return 0; diff --git a/xen/drivers/vpci/vpci.c b/xen/drivers/vpci/vpci.c index 3bec9a4153da..8b26870a8a2b 100644 --- a/xen/drivers/vpci/vpci.c +++ b/xen/drivers/vpci/vpci.c @@ -29,6 +29,7 @@ struct vpci_register { unsigned int offset; void *private; struct list_head node; + uint32_t rw1c_mask; }; #ifdef __XEN__ @@ -145,9 +146,15 @@ uint32_t cf_check vpci_hw_read32( return pci_conf_read32(pdev->sbdf, reg); } -int vpci_add_register(struct vpci *vpci, vpci_read_t *read_handler, - vpci_write_t *write_handler, unsigned int offset, - unsigned int size, void *data) +void cf_check vpci_hw_write16( + const struct pci_dev *pdev, unsigned int reg, uint32_t val, void *data) +{ + pci_conf_write16(pdev->sbdf, reg, val); +} + +static int add_register(struct vpci *vpci, vpci_read_t *read_handler, + vpci_write_t *write_handler, unsigned int offset, + unsigned int size, void *data, uint32_t rw1c_mask) { struct list_head *prev; struct vpci_register *r; @@ -167,6 +174,7 @@ int vpci_add_register(struct vpci *vpci, vpci_read_t *read_handler, r->size = size; r->offset = offset; r->private = data; + r->rw1c_mask = rw1c_mask; spin_lock(&vpci->lock); @@ -193,6 +201,22 @@ int vpci_add_register(struct vpci *vpci, vpci_read_t *read_handler, return 0; } +int vpci_add_register(struct vpci *vpci, vpci_read_t *read_handler, + vpci_write_t *write_handler, unsigned int offset, + unsigned int size, void *data) +{ + return add_register(vpci, read_handler, write_handler, offset, size, data, + 0); +} + +int vpci_add_rw1c_register(struct vpci *vpci, vpci_read_t *read_handler, + vpci_write_t *write_handler, unsigned int offset, + unsigned int size, void *data, uint32_t rw1c_mask) +{ + return add_register(vpci, read_handler, write_handler, offset, size, data, + rw1c_mask); +} + int vpci_remove_register(struct vpci *vpci, unsigned int offset, unsigned int size) { @@ -407,11 +431,6 @@ uint32_t vpci_read(pci_sbdf_t sbdf, unsigned int reg, unsigned int size) /* * Perform a maybe partial write to a register. - * - * Note that this will only work for simple registers, if Xen needs to - * trap accesses to rw1c registers (like the status PCI header register) - * the logic in vpci_write will have to be expanded in order to correctly - * deal with them. */ static void vpci_write_helper(const struct pci_dev *pdev, const struct vpci_register *r, unsigned int size, @@ -424,6 +443,7 @@ static void vpci_write_helper(const struct pci_dev *pdev, uint32_t val; val = r->read(pdev, r->offset, r->private); + val &= ~r->rw1c_mask; data = merge_result(val, data, size, offset); } diff --git a/xen/include/xen/vpci.h b/xen/include/xen/vpci.h index 0b8a2a3c745b..51b1b06c2c71 100644 --- a/xen/include/xen/vpci.h +++ b/xen/include/xen/vpci.h @@ -37,6 +37,11 @@ int __must_check vpci_add_register(struct vpci *vpci, vpci_write_t *write_handler, unsigned int offset, unsigned int size, void *data); +int __must_check vpci_add_rw1c_register(struct vpci *vpci, + vpci_read_t *read_handler, + vpci_write_t *write_handler, + unsigned int offset, unsigned int size, + void *data, uint32_t rw1c_mask); int __must_check vpci_remove_register(struct vpci *vpci, unsigned int offset, unsigned int size); @@ -50,6 +55,8 @@ uint32_t cf_check vpci_hw_read16( const struct pci_dev *pdev, unsigned int reg, void *data); uint32_t cf_check vpci_hw_read32( const struct pci_dev *pdev, unsigned int reg, void *data); +void cf_check vpci_hw_write16( + const struct pci_dev *pdev, unsigned int reg, uint32_t val, void *data); /* * Check for pending vPCI operations on this vcpu. Returns true if the vcpu @@ -94,6 +101,8 @@ struct vpci { * upon to know whether BARs are mapped into the guest p2m. */ bool bars_mapped : 1; + /* Store whether to hide all capabilities from the guest. */ + bool mask_cap_list : 1; /* FIXME: currently there's no support for SR-IOV. */ } header;