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pr=C From: Ayan Kumar Halder To: CC: , , , , , , , , Ayan Kumar Halder Subject: [XEN v1 4/4] xen/arm: traps.c: Enclose VMSA specific registers within CONFIG_MMU Date: Mon, 11 Sep 2023 14:59:42 +0100 Message-ID: <20230911135942.791206-5-ayan.kumar.halder@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230911135942.791206-1-ayan.kumar.halder@amd.com> References: <20230911135942.791206-1-ayan.kumar.halder@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS2PEPF00003444:EE_|CH2PR12MB4328:EE_ X-MS-Office365-Filtering-Correlation-Id: 8a7c3af5-8f2e-4ce6-4edd-08dbb2cf8774 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 5jMevpm3KxWfY2402R2YnZOkislKOztc59g7u2ezdcagfiE8l4fezFotJT/nssRSwW4X5sfPHCAARJEQX6Eb7mE7B1EbCRAwCEPhHD7sAoWbDatwoi8mi6vIAXtpwsCepzG+1Sj6ENwxYbYAYRRcnYgy/vZZQaDfVMLgD+qJ3NiQCOlOr9uTTqDRO3LbDABIEIaKUu9uVm4BHbzXe3rOWMuVlDjBXDLrAdY93IqBZQmlwvm5O7BY3gJz9Ibweb0mMT75RlGJlbCv31IUhcgfUH/yKo358EAwJDtW3XO8VmqWyKbpBI1/Oo2Pkc0GmcgQZ9w/HLKleh0gk4axzpb53Heucgidv9VydB6HbPBwgHLu4emnpQDjAQkeNIxC9lYMlTy1L3zxuG8ZPafA6LAG79h/t5rIYz5kx76WHqThr6WNJng5TuRN+5IJKwZU1x+GwE0AhS+IzhvX+jd9TNZh2C7HKkJzYnddNOTDR700f+1Uh2oS07U1rCbVwe5TbZMi+NIx1sMmbsmBPRQvvD0KlIqhxQcp1TssHE+1KqFbXKuR2fc9+VgJgDL8INM1a2AQN48yttr5obTJYqTTdVVbnIbLqrcJLCux/zr9n1DmMBax41NgvnrxE2Opsaw48W1W9aAgQlnQBGzhRX66qlp1CpeXXojLFTRSjk/2fLohG6u8zYZWb0NHxaX9+URNc7eDdV2eSnYjn2AVtCH4lAgrB5AkmUtkYjqm9o/CbY7f1addM507pvgKMI8Rww4jdf0L0O5NEAbWKJO8FWCDCMH0QA== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230031)(4636009)(346002)(396003)(39860400002)(136003)(376002)(1800799009)(82310400011)(186009)(451199024)(46966006)(36840700001)(40470700004)(70586007)(26005)(86362001)(1076003)(426003)(336012)(2906002)(83380400001)(103116003)(6666004)(40480700001)(2616005)(36860700001)(356005)(82740400003)(81166007)(47076005)(40460700003)(478600001)(36756003)(5660300002)(4326008)(8936002)(8676002)(316002)(54906003)(6916009)(70206006)(41300700001)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 11 Sep 2023 14:01:00.2796 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 8a7c3af5-8f2e-4ce6-4edd-08dbb2cf8774 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DS2PEPF00003444.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH2PR12MB4328 The VMSA specific registers (ie TCR, TTBR0, TTBR1, VTTBR, etc) are valid when MMU is used, thus we can enclose them with CONFIG_MMU. Signed-off-by: Ayan Kumar Halder --- xen/arch/arm/traps.c | 17 +++++++++++++++-- 1 file changed, 15 insertions(+), 2 deletions(-) diff --git a/xen/arch/arm/traps.c b/xen/arch/arm/traps.c index 46c9a4031b..83522fcc5a 100644 --- a/xen/arch/arm/traps.c +++ b/xen/arch/arm/traps.c @@ -698,8 +698,10 @@ static void __do_trap_serror(struct cpu_user_regs *regs, bool guest) struct reg_ctxt { /* Guest-side state */ register_t sctlr_el1; +#ifdef CONFIG_MMU register_t tcr_el1; uint64_t ttbr0_el1, ttbr1_el1; +#endif #ifdef CONFIG_ARM_32 uint32_t dfsr, ifsr; uint32_t dfar, ifar; @@ -801,9 +803,11 @@ static void show_registers_32(const struct cpu_user_regs *regs, if ( guest_mode_on ) { printk(" SCTLR: %"PRIregister"\n", ctxt->sctlr_el1); +#ifdef CONFIG_MMU printk(" TCR: %"PRIregister"\n", ctxt->tcr_el1); printk(" TTBR0: %016"PRIx64"\n", ctxt->ttbr0_el1); printk(" TTBR1: %016"PRIx64"\n", ctxt->ttbr1_el1); +#endif printk(" IFAR: %08"PRIx32", IFSR: %08"PRIx32"\n" " DFAR: %08"PRIx32", DFSR: %08"PRIx32"\n", #ifdef CONFIG_ARM_64 @@ -873,9 +877,11 @@ static void show_registers_64(const struct cpu_user_regs *regs, printk(" FAR_EL1: %016"PRIx64"\n", ctxt->far); printk("\n"); printk(" SCTLR_EL1: %"PRIregister"\n", ctxt->sctlr_el1); +#ifdef CONFIG_MMU printk(" TCR_EL1: %"PRIregister"\n", ctxt->tcr_el1); printk(" TTBR0_EL1: %016"PRIx64"\n", ctxt->ttbr0_el1); printk(" TTBR1_EL1: %016"PRIx64"\n", ctxt->ttbr1_el1); +#endif printk("\n"); } } @@ -907,13 +913,15 @@ static void _show_registers(const struct cpu_user_regs *regs, show_registers_32(regs, ctxt, guest_mode_on, v); #endif } +#ifdef CONFIG_MMU printk(" VTCR_EL2: %"PRIregister"\n", READ_SYSREG(VTCR_EL2)); printk(" VTTBR_EL2: %016"PRIx64"\n", ctxt->vttbr_el2); + printk(" TTBR0_EL2: %016"PRIx64"\n", READ_SYSREG64(TTBR0_EL2)); printk("\n"); +#endif printk(" SCTLR_EL2: %"PRIregister"\n", READ_SYSREG(SCTLR_EL2)); printk(" HCR_EL2: %"PRIregister"\n", READ_SYSREG(HCR_EL2)); - printk(" TTBR0_EL2: %016"PRIx64"\n", READ_SYSREG64(TTBR0_EL2)); printk("\n"); printk(" ESR_EL2: %"PRIregister"\n", regs->hsr); printk(" HPFAR_EL2: %"PRIregister"\n", READ_SYSREG(HPFAR_EL2)); @@ -931,9 +939,13 @@ void show_registers(const struct cpu_user_regs *regs) { struct reg_ctxt ctxt; ctxt.sctlr_el1 = READ_SYSREG(SCTLR_EL1); +#ifdef CONFIG_MMU ctxt.tcr_el1 = READ_SYSREG(TCR_EL1); ctxt.ttbr0_el1 = READ_SYSREG64(TTBR0_EL1); ctxt.ttbr1_el1 = READ_SYSREG64(TTBR1_EL1); + ctxt.vttbr_el2 = READ_SYSREG64(VTTBR_EL2); +#endif + #ifdef CONFIG_ARM_32 ctxt.dfar = READ_CP32(DFAR); ctxt.ifar = READ_CP32(IFAR); @@ -945,7 +957,6 @@ void show_registers(const struct cpu_user_regs *regs) if ( guest_mode(regs) && is_32bit_domain(current->domain) ) ctxt.ifsr32_el2 = READ_SYSREG(IFSR32_EL2); #endif - ctxt.vttbr_el2 = READ_SYSREG64(VTTBR_EL2); _show_registers(regs, &ctxt, guest_mode(regs), current); } @@ -954,9 +965,11 @@ void vcpu_show_registers(const struct vcpu *v) { struct reg_ctxt ctxt; ctxt.sctlr_el1 = v->arch.sctlr; +#ifdef CONFIG_MMU ctxt.tcr_el1 = v->arch.ttbcr; ctxt.ttbr0_el1 = v->arch.ttbr0; ctxt.ttbr1_el1 = v->arch.ttbr1; +#endif #ifdef CONFIG_ARM_32 ctxt.dfar = v->arch.dfar; ctxt.ifar = v->arch.ifar;