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[46.102.197.194]) by smtp.gmail.com with ESMTPSA id ah2-20020a1709069ac200b00a4e393b6349sm13898875ejc.5.2024.04.29.08.16.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 29 Apr 2024 08:16:31 -0700 (PDT) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 7609761f-063b-11ef-b4bb-af5377834399 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=citrix.com; s=google; t=1714403792; x=1715008592; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=CV04Tx+6NsZ8X0U2ufYfuFomh7VBRRmRmAKxgTh3wY4=; b=ul+veVfYxeRnBYKuGh62tNF+dlxekK+jLbnkK6MN773QU4zcOvQQ9Yqa4o9jMhxE5C IgTtHGNf6osYaGywVnEJqpAMG3wBqKxqhZAIARBqwZx4MK+KTKXjN50gwQ2zccOhx1pL vVWEmhedBsP7GQPJDF7kRVgwHDen4H8+ru69M= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1714403792; x=1715008592; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=CV04Tx+6NsZ8X0U2ufYfuFomh7VBRRmRmAKxgTh3wY4=; b=ic+/xL0VlPR4qI3dJ+s2ttKmKREwSrnUjYdG6LCC0VgNDwrU7uWbNEnafpafvxduQg hXjuGIYzm6C2n9QIBBMP0taJqZHMlC4JSniKQSXbYa5u3cfTvOwMA5wrbgkVvbzljMyj 3kenc2Ae9nevkF8oeAZpLTwRLPWkjK6XVs8JEhuPHVCv/s7glK+4mOqHETKYEWh9CX0i JWJFxKhXuXFvO1wOGO6TT3wfejVeTaarwBSYp8MpxiQ1HI1Y6ETUBlFsBx3Q/wECHzmw 6911o08F5xcComTjvFPMLYZ797UbDn9Notd1cG14IGoWrLgvkHzZVKfObSTmURJveHXe r6qg== X-Gm-Message-State: AOJu0YwJeBDaldc4+TKYMUkni8+YszbHjkJNA4NvYbdHtmgDZGfjS2YH ncrU5FwiWwNdv4OtGySIIBwtadE4XLHnBTo0YvDJOzKKffikAG3/aeiYkrU8d2S3nMn0S4rQwew T X-Google-Smtp-Source: AGHT+IGO5TKFQYD+gTBIWeGVUOgzvtYEWbvErapDz4z7ZkjskrEyh/eDv+ptI2Mb53VrbReYfmobjw== X-Received: by 2002:a17:906:480f:b0:a58:8a33:1a39 with SMTP id w15-20020a170906480f00b00a588a331a39mr9853087ejq.3.1714403791795; Mon, 29 Apr 2024 08:16:31 -0700 (PDT) From: Andrew Cooper To: Xen-devel Cc: Andrew Cooper , Jan Beulich , =?utf-8?q?Roger_Pau_Monn=C3=A9?= , Stefano Stabellini , Xenia Ragiadakou , Sergiy Kibrik , George Dunlap , Andrei Semenov , Vaishali Thakkar Subject: [PATCH 5/5] x86/cpu-policy: Introduce some SEV features Date: Mon, 29 Apr 2024 16:16:25 +0100 Message-Id: <20240429151625.977884-6-andrew.cooper3@citrix.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20240429151625.977884-1-andrew.cooper3@citrix.com> References: <20240429151625.977884-1-andrew.cooper3@citrix.com> MIME-Version: 1.0 For display purposes only right now. Signed-off-by: Andrew Cooper Reviewed-by: Vaishali Thakkar Reviewed-by: Jan Beulich --- CC: Jan Beulich CC: Roger Pau Monné CC: Stefano Stabellini CC: Xenia Ragiadakou CC: Sergiy Kibrik CC: George Dunlap CC: Andrei Semenov CC: Vaishali Thakkar This is only half the work to get SEV working nicely. The other half (rearranging __start_xen() so we can move the host policy collection earlier) is still a work-in-progress. --- tools/misc/xen-cpuid.c | 3 +++ xen/arch/x86/include/asm/cpufeature.h | 3 +++ xen/include/public/arch-x86/cpufeatureset.h | 4 ++++ xen/tools/gen-cpuid.py | 6 +++++- 4 files changed, 15 insertions(+), 1 deletion(-) diff --git a/tools/misc/xen-cpuid.c b/tools/misc/xen-cpuid.c index 0d01b0e797f1..1463e0429ba1 100644 --- a/tools/misc/xen-cpuid.c +++ b/tools/misc/xen-cpuid.c @@ -281,6 +281,9 @@ static const char *const str_eAd[32] = static const char *const str_e1Fa[32] = { + [ 0] = "sme", [ 1] = "sev", + /* 2 */ [ 3] = "sev-es", + [ 4] = "sev-snp", }; static const struct { diff --git a/xen/arch/x86/include/asm/cpufeature.h b/xen/arch/x86/include/asm/cpufeature.h index b6fb8c24423c..732f0d2bf758 100644 --- a/xen/arch/x86/include/asm/cpufeature.h +++ b/xen/arch/x86/include/asm/cpufeature.h @@ -230,6 +230,9 @@ static inline bool boot_cpu_has(unsigned int feat) #define cpu_has_v_gif boot_cpu_has(X86_FEATURE_V_GIF) #define cpu_has_v_spec_ctrl boot_cpu_has(X86_FEATURE_V_SPEC_CTRL) +/* CPUID level 0x8000001f.eax */ +#define cpu_has_sev boot_cpu_has(X86_FEATURE_SEV) + /* Synthesized. */ #define cpu_has_arch_perfmon boot_cpu_has(X86_FEATURE_ARCH_PERFMON) #define cpu_has_cpuid_faulting boot_cpu_has(X86_FEATURE_CPUID_FAULTING) diff --git a/xen/include/public/arch-x86/cpufeatureset.h b/xen/include/public/arch-x86/cpufeatureset.h index 80d252a38c2d..7ee0f2329151 100644 --- a/xen/include/public/arch-x86/cpufeatureset.h +++ b/xen/include/public/arch-x86/cpufeatureset.h @@ -374,6 +374,10 @@ XEN_CPUFEATURE(NPT_SSS, 18*32+19) /* NPT Supervisor Shadow Stacks * XEN_CPUFEATURE(V_SPEC_CTRL, 18*32+20) /* Virtualised MSR_SPEC_CTRL */ /* AMD-defined CPU features, CPUID level 0x8000001f.eax, word 19 */ +XEN_CPUFEATURE(SME, 19*32+ 0) /* Secure Memory Encryption */ +XEN_CPUFEATURE(SEV, 19*32+ 1) /* Secure Encryped VM */ +XEN_CPUFEATURE(SEV_ES, 19*32+ 3) /* SEV Encrypted State */ +XEN_CPUFEATURE(SEV_SNP, 19*32+ 4) /* SEV Secure Nested Paging */ #endif /* XEN_CPUFEATURE */ diff --git a/xen/tools/gen-cpuid.py b/xen/tools/gen-cpuid.py index f07b1f4cf905..bff4d9389ff6 100755 --- a/xen/tools/gen-cpuid.py +++ b/xen/tools/gen-cpuid.py @@ -281,7 +281,7 @@ def crunch_numbers(state): _3DNOW: [_3DNOWEXT], # The SVM bit enumerates the whole SVM leave. - SVM: list(range(NPT, NPT + 32)), + SVM: list(range(NPT, NPT + 32)) + [SEV], # This is just the dependency between AVX512 and AVX2 of XSTATE # feature flags. If want to use AVX512, AVX2 must be supported and @@ -341,6 +341,10 @@ def crunch_numbers(state): # The behaviour described by RRSBA depend on eIBRS being active. EIBRS: [RRSBA], + + SEV: [SEV_ES], + + SEV_ES: [SEV_SNP], } deep_features = tuple(sorted(deps.keys()))