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pr=C From: Ayan Kumar Halder To: , , , , , CC: Subject: [PATCH v2 4/4] xen: arm: Enclose access to EL2 MMU specific registers under CONFIG_MMU Date: Thu, 8 Aug 2024 13:09:36 +0100 Message-ID: <20240808120936.3299937-5-ayan.kumar.halder@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240808120936.3299937-1-ayan.kumar.halder@amd.com> References: <20240808120936.3299937-1-ayan.kumar.halder@amd.com> MIME-Version: 1.0 Received-SPF: None (SATLEXMB05.amd.com: ayan.kumar.halder@amd.com does not designate permitted sender hosts) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1PEPF000042A7:EE_|BY5PR12MB4305:EE_ X-MS-Office365-Filtering-Correlation-Id: 68d8ef76-460a-41db-5f86-08dcb7a301f4 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|1800799024|376014|82310400026; X-Microsoft-Antispam-Message-Info: MI8MmMqeoVjtpEdvNxnlJ/tgHRZwZyB6P5hoFdvR2EAEBVSCZ22vCX7ovw3wAVBOP0/47TSXx/97XXpFwJqjsOh/bv0sEqLSJ5N5n/zwUc0n4Uv3vM2LuylskrctT2FCdt1zKry+s3tFKx8BjYjCEhxWFLwyA15OM56BojAuKYr97vOdwK7hxVsECwtC+VafwCmeHbx/Z5r5ycHIz9wGz5Ngn4GCKnBuso6p+NhHUtrlQZFz2eMPGX+nm0zXUjGhDWezP1cRz/fyNjrptl2amRuvNVeZ1ba2lhfDbqk0/jTfhSLYzab0uakgZmIDiWSx/j0Gmcn6vkxX7aX20U5haJHCXevDAgbWUCRBqu7u3IZOQt64u90jCxxYoUH7rvAdmNBkLGPifmWzwXWxf5EMk8RZG5ZBFE82xnIbjVx/NdxOZ0p9uf3/CF3YocFxkjrDZ+yb5KJOvrH2cKq8c3Pbu14sHaNvNgOi3YWgoC1+VHyxez6I2tOzX4rBKSbL/lD1LVSH6dBboWa6ETCOCQI6Ktev7LA+PbOR2W07/8barXyHpKkEgdOOE0KYaFJOSLBOfhylIaL7QuzkiyqMqZw1xF3/Uaz1DrfpE83RcRPZ+JjD6wWIVUGwo7G3GAQdcBKJuIXUzqH9Gz/J0EGHawi7djm+CjToPUuESWN6Qj2K52K/AVR/4dHoOWqSxrFAzKXMo8y8dQDxxQp6gTwS7Ey6XyUCiOGqfQ6g1RXWR5yExwPKhE6lT2X+zqRk2YjET9x4JYZelZh08p4SPGJex6QhWxVJmPp2Sl1Sgm8eZs3F3lhzOragVikmLiV7BrVi6AaiuRJQFeLFyQ01Cx+KQ21SjzdoUexTqURMAKsKESEbMNhBndPYqMkCR2zzY5vAh08hmTN76RAk8locP2PcIB6WCK3raEgeRQovDLyHxaNiG1bfEvjVsde8uzhE4qDXFI2Mb9VpgfJT4PpilbrTrPZ4GB9GDHG21Z9WE9XAr4JVFU0BNJD9On4C8t8suoq8ucAlvb1t5z2RMkbICX7hDMnh29ZqL2ZaX/bdUz5uknxOyasmsuwjax25xoOhAZAXOGPWE+8NAwutW9IbabrmQ7p1NZYAdohxYtJPDt3CRHY0AwntQJDpjE/iilLJxvoIIJhvlSbBsYUiupkwC98qun4Vfty6mCZ5nJP1zMdnTbd3l0Jdg/v90BaQAPnGFSj4RA2o6QIB1alszCO/SZpV5KQ1TXaJA3bWQqRLGajBwfGCDsDXoQnu+hFed35HbMKT81DkTFn5pi2bMPMyWY6xMcodBWi4AevbxoSOkFu5/18RYwWhZERGuDVP0fo64/mvCrv128iEsvtkLoNS/HTL5tK6/rogSdLZGDRO45cC4o+b/5jkF4VWnbBZ9LFEWdZfJia1dYY40xrRBMmq8TiuX5y1JOcQ+bVXKPnPy5V19O0/vpVhpLQSTnay6C5yEEMP8BrK X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB03.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(36860700013)(1800799024)(376014)(82310400026);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Aug 2024 12:09:51.8237 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 68d8ef76-460a-41db-5f86-08dcb7a301f4 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1PEPF000042A7.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY5PR12MB4305 All the EL2 MMU specific registers are enclosed within CONFIG_MMU. Signed-off-by: Ayan Kumar Halder --- Changes from v1 :- 1. 'vttbr_el2' field is enclosed with ifdef. 2. No movement of code. xen/arch/arm/traps.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/xen/arch/arm/traps.c b/xen/arch/arm/traps.c index aac6c599f8..f51e1424cb 100644 --- a/xen/arch/arm/traps.c +++ b/xen/arch/arm/traps.c @@ -720,8 +720,10 @@ struct reg_ctxt { uint32_t ifsr32_el2; #endif +#ifdef CONFIG_MMU /* Hypervisor-side state */ uint64_t vttbr_el2; +#endif }; static const char *mode_string(register_t cpsr) @@ -919,12 +921,16 @@ static void _show_registers(const struct cpu_user_regs *regs, #endif } printk(" VTCR_EL2: %"PRIregister"\n", READ_SYSREG(VTCR_EL2)); +#ifdef CONFIG_MMU printk(" VTTBR_EL2: %016"PRIx64"\n", ctxt->vttbr_el2); +#endif printk("\n"); printk(" SCTLR_EL2: %"PRIregister"\n", READ_SYSREG(SCTLR_EL2)); printk(" HCR_EL2: %"PRIregister"\n", READ_SYSREG(HCR_EL2)); +#ifdef CONFIG_MMU printk(" TTBR0_EL2: %016"PRIx64"\n", READ_SYSREG64(TTBR0_EL2)); +#endif printk("\n"); printk(" ESR_EL2: %"PRIregister"\n", regs->hsr); printk(" HPFAR_EL2: %"PRIregister"\n", READ_SYSREG(HPFAR_EL2));