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pr=C From: Jason Andryuk To: Juergen Gross , Boris Ostrovsky , Thomas Gleixner , "Ingo Molnar" , Borislav Petkov , Dave Hansen , , "H. Peter Anvin" , Stefano Stabellini , "Oleksandr Tyshchenko" , Paolo Bonzini , Brian Gerst CC: , , "Jason Andryuk" Subject: [PATCH v2 2/5] x86/pvh: Make PVH entrypoint PIC for x86-64 Date: Wed, 14 Aug 2024 15:50:50 -0400 Message-ID: <20240814195053.5564-3-jason.andryuk@amd.com> X-Mailer: git-send-email 2.46.0 In-Reply-To: <20240814195053.5564-1-jason.andryuk@amd.com> References: <20240814195053.5564-1-jason.andryuk@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1PEPF000044F7:EE_|CY5PR12MB6384:EE_ X-MS-Office365-Filtering-Correlation-Id: f8d40ee4-e912-4ded-44d1-08dcbc9a6d40 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|1800799024|82310400026|7416014|376014|921020; X-Microsoft-Antispam-Message-Info: b5fG4thVHpJa8UBCnUBBURbKKrtZ9+8rNhat9p7NjhKvaO0QpxDzmCEIH0ezbRop2WDvuY5lOBZTNOu2KqnHDR0vc5bZNGJW15cv7tn+iP0WfUD//eUBnNQ+kpLIAgr0fkX9SGXMgReCz5vCfl89zsrahxHS6j7vD6paZXRa90Rh4RBZEgjGRZrnihOOwXFbIG87amymTi3cAhZTwCkSJ/RbIxbCLRBZh59cjlFi2IpNSdD7Jrj90dKr476tys7q4tDFl9h+aIK4sOFXYZa4YAW0XcZNU8ejBJAWRfMCRNddSjviAZlkGH9qjLfZ1PtmZHeoh3FPlnpIz/crQp5IQecQbEWTKNKNZbxSzlzwvl7e93yzk4op+ZJhx65DvRCzAAwxFMQgUk3o9HqrC1rP5cJzOatlHiAhAM2zwatF7tqEAem8bg34/8zg4g0CzT4RHWD9J49JGHs8LGSUFWhAl3XcUT00eZFFryWrCYNzPTTqfEvlp93fpCmwwLh4Avus7pJHuSxnx5xpJ1f5FISR4na+aGwjuCAvze4MdGlyIB+dbabjigQ813WoSPsi1/gcb3Vs2DZyV148N6PMJzsrGG2TVxQ6zg1pzT0XCIWdmsYGPOp4bERQPDiczsAENmwUA+RCFCSaJDJFXmB12TbmhlJDAaoQLZDsUapt5IhTxithiXSqYo3lcyYORMs9TrfddWVlV3etu2SFlKtwK4WgFUtTbsYdBwfuNoradvKbriUHKPoNf1N0rZ2Wl9UF/1ZhV/CylbJUPWiQieFmbCdXlUX3gv1rz6MBGvSdSZyzjgcAoDsDjtMP83Andl20RxRmMp67Oeyz+AeM+AZYa2rgfW8VfFimumvJ0bHyrIRilnH4XBdaeT8Ch1C/dm7gWWRJQC7DXDMJQWsjHk7/ZZd51bmsIWDdkQMxupzYbySzU+17FLA6QY/j9zbNEfAd1owW5+oiyifA4bVmHHgdHJ4kp27VXTDJyvWLLNJDfnKXm8QhfwO42D2MgSAT4hYt+3OhnjTBwqEGYGKaP4VcJWj/DC4iel3kIWX0949Hhv2MYz6xkHbM8aST2W+xml/Lh0HvO1UWAdxVHoOL+DKwCynjsaPGADLfbB9ri5DGZqkkcrIQEq3N6e+n5sgfrgYehQCvdn+kp5tK6QnSxpGTcfA+Cxy3/H+7D2Wd5CAj5/SRt5GHM/s5EE9JNoYu5RZR0L08nJvNfMLZf4V3CERfssJsmNlQySpSfhNvyL3AQRSdl7qROuimx3pY40hB63zfD+nOFSWSrHOkp6d3CfgK/SQqzCACqsDK2yyfOdy1g/ojyYg+TrTN0LWwqx8+Fh6tvBpJby03OyyfS/U/EHuTNDqDjw1ybdne6qhDcN4xrVkr/p6x0/rsWaD94w44s5qaPECeBlk1ln/G9PXNdelkA1OsC7ecfVK7lNpVzV3liZNppTISEHEScOAvWXhalipSRoYUPu5suOlW5rPJlEOrjGZnOQ== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(36860700013)(1800799024)(82310400026)(7416014)(376014)(921020);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 14 Aug 2024 19:51:02.1650 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: f8d40ee4-e912-4ded-44d1-08dcbc9a6d40 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1PEPF000044F7.namprd21.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY5PR12MB6384 The PVH entrypoint is 32bit non-PIC code running the uncompressed vmlinux at its load address CONFIG_PHYSICAL_START - default 0x1000000 (16MB). The kernel is loaded at that physical address inside the VM by the VMM software (Xen/QEMU). When running a Xen PVH Dom0, the host reserved addresses are mapped 1-1 into the PVH container. There exist system firmwares (Coreboot/EDK2) with reserved memory at 16MB. This creates a conflict where the PVH kernel cannot be loaded at that address. Modify the PVH entrypoint to be position-indepedent to allow flexibility in load address. Only the 64bit entry path is converted. A 32bit kernel is not PIC, so calling into other parts of the kernel, like xen_prepare_pvh() and mk_pgtable_32(), don't work properly when relocated. This makes the code PIC, but the page tables need to be updated as well to handle running from the kernel high map. The UNWIND_HINT_END_OF_STACK is to silence: vmlinux.o: warning: objtool: pvh_start_xen+0x7f: unreachable instruction after the lret into 64bit code. Signed-off-by: Jason Andryuk --- v2: Use rip-relative loads in 64bit mode Direct jmp to startup_64 --- arch/x86/platform/pvh/head.S | 46 ++++++++++++++++++++++++++---------- 1 file changed, 34 insertions(+), 12 deletions(-) diff --git a/arch/x86/platform/pvh/head.S b/arch/x86/platform/pvh/head.S index f7235ef87bc3..ba4d0eab4436 100644 --- a/arch/x86/platform/pvh/head.S +++ b/arch/x86/platform/pvh/head.S @@ -7,6 +7,7 @@ .code32 .text #define _pa(x) ((x) - __START_KERNEL_map) +#define rva(x) ((x) - pvh_start_xen) #include #include @@ -54,7 +55,25 @@ SYM_CODE_START_LOCAL(pvh_start_xen) UNWIND_HINT_END_OF_STACK cld - lgdt (_pa(gdt)) + /* + * See the comment for startup_32 for more details. We need to + * execute a call to get the execution address to be position + * independent, but we don't have a stack. Save and restore the + * magic field of start_info in ebx, and use that as the stack. + */ + mov (%ebx), %eax + leal 4(%ebx), %esp + ANNOTATE_INTRA_FUNCTION_CALL + call 1f +1: popl %ebp + mov %eax, (%ebx) + subl $rva(1b), %ebp + movl $0, %esp + + leal rva(gdt)(%ebp), %eax + leal rva(gdt_start)(%ebp), %ecx + movl %ecx, 2(%eax) + lgdt (%eax) mov $PVH_DS_SEL,%eax mov %eax,%ds @@ -62,14 +81,14 @@ SYM_CODE_START_LOCAL(pvh_start_xen) mov %eax,%ss /* Stash hvm_start_info. */ - mov $_pa(pvh_start_info), %edi + leal rva(pvh_start_info)(%ebp), %edi mov %ebx, %esi - mov _pa(pvh_start_info_sz), %ecx + movl rva(pvh_start_info_sz)(%ebp), %ecx shr $2,%ecx rep movsl - mov $_pa(early_stack_end), %esp + leal rva(early_stack_end)(%ebp), %esp /* Enable PAE mode. */ mov %cr4, %eax @@ -84,30 +103,33 @@ SYM_CODE_START_LOCAL(pvh_start_xen) wrmsr /* Enable pre-constructed page tables. */ - mov $_pa(init_top_pgt), %eax + leal rva(init_top_pgt)(%ebp), %eax mov %eax, %cr3 mov $(X86_CR0_PG | X86_CR0_PE), %eax mov %eax, %cr0 /* Jump to 64-bit mode. */ - ljmp $PVH_CS_SEL, $_pa(1f) + pushl $PVH_CS_SEL + leal rva(1f)(%ebp), %eax + pushl %eax + lretl /* 64-bit entry point. */ .code64 1: + UNWIND_HINT_END_OF_STACK + /* Set base address in stack canary descriptor. */ mov $MSR_GS_BASE,%ecx - mov $_pa(canary), %eax + leal canary(%rip), %eax xor %edx, %edx wrmsr call xen_prepare_pvh /* startup_64 expects boot_params in %rsi. */ - mov $_pa(pvh_bootparams), %rsi - mov $_pa(startup_64), %rax - ANNOTATE_RETPOLINE_SAFE - jmp *%rax + lea pvh_bootparams(%rip), %rsi + jmp startup_64 #else /* CONFIG_X86_64 */ @@ -143,7 +165,7 @@ SYM_CODE_END(pvh_start_xen) .balign 8 SYM_DATA_START_LOCAL(gdt) .word gdt_end - gdt_start - .long _pa(gdt_start) + .long _pa(gdt_start) /* x86-64 will overwrite if relocated. */ .word 0 SYM_DATA_END(gdt) SYM_DATA_START_LOCAL(gdt_start)