diff mbox series

[RFC,DONOTMERGE,1/1] arm64: dts: ti: k3-am62p-main: Add interrupts property for DMSS INTA

Message ID 20240903083107.3562816-2-vaishnav.a@ti.com (mailing list archive)
State New
Headers show
Series Add interrupts property to interrupt aggregators/routers | expand

Commit Message

Vaishnav Achath Sept. 3, 2024, 8:31 a.m. UTC 
The interrupt aggregator in DMSS for TI K3 devices currently uses a
custom vendor property "ti,interrupt-ranges" to specify the interrupt
source to parent mapping. As per interrupt controller bindings [1],
it is mandatory for Nodes that describe devices which generate
interrupts to contain an "interrupts" property, an "interrupts-extended"
property, or both. Add interrupts property to the Interrupt aggregator
node so that the mapping is specified in a standard manner.

1 - https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/devicetree/bindings/interrupt-controller/interrupts.txt

Signed-off-by: Vaishnav Achath <vaishnav.a@ti.com>
---

DONOTMERGE - while adding the interrupts property helps to conform to the
bindings, it is difficult to maintain the long list and this is not the only
platform affected, if this is the direction to fix it, I will fix for all K3
platforms together, more details on RFC in cover letter.

 arch/arm64/boot/dts/ti/k3-am62p-main.dtsi | 35 +++++++++++++++++++++++
 1 file changed, 35 insertions(+)
diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/ti/k3-am62p-main.dtsi b/arch/arm64/boot/dts/ti/k3-am62p-main.dtsi
index 420c77c8e9e5..0c7912d177fe 100644
--- a/arch/arm64/boot/dts/ti/k3-am62p-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am62p-main.dtsi
@@ -40,6 +40,41 @@  &oc_sram {
 
 &inta_main_dmss {
 	ti,interrupt-ranges = <5 69 35>;
+	interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
+		     <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
+		     <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
+		     <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
+		     <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
+		     <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
+		     <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
+		     <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
+		     <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
+		     <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
+		     <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
+		     <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
+		     <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
+		     <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
+		     <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
+		     <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
+		     <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
+		     <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
+		     <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
+		     <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
+		     <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
+		     <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
+		     <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
+		     <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
+		     <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
+		     <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
+		     <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>,
+		     <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
+		     <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
+		     <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
+		     <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
+		     <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
+		     <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
+		     <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
+		     <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
 };
 
 &main_pmx0 {