From patchwork Wed Sep 18 09:15:17 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sergiy Kibrik X-Patchwork-Id: 13806727 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id BFEC7CCD192 for ; Wed, 18 Sep 2024 09:15:54 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.800200.1210090 (Exim 4.92) (envelope-from ) id 1sqqmW-0007qH-QI; Wed, 18 Sep 2024 09:15:28 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 800200.1210090; Wed, 18 Sep 2024 09:15:28 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1sqqmW-0007qA-No; Wed, 18 Sep 2024 09:15:28 +0000 Received: by outflank-mailman (input) for mailman id 800200; Wed, 18 Sep 2024 09:15:27 +0000 Received: from se1-gles-flk1-in.inumbo.com ([94.247.172.50] helo=se1-gles-flk1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1sqqmV-0007q3-9j for xen-devel@lists.xenproject.org; Wed, 18 Sep 2024 09:15:27 +0000 Received: from pb-smtp2.pobox.com (pb-smtp2.pobox.com [64.147.108.71]) by se1-gles-flk1.inumbo.com (Halon) with ESMTPS id 87a46fe6-759e-11ef-99a2-01e77a169b0f; Wed, 18 Sep 2024 11:15:23 +0200 (CEST) Received: from pb-smtp2.pobox.com (unknown [127.0.0.1]) by pb-smtp2.pobox.com (Postfix) with ESMTP id E30E930FB5; Wed, 18 Sep 2024 05:15:20 -0400 (EDT) (envelope-from sakib@darkstar.site) Received: from pb-smtp2.nyi.icgroup.com (unknown [127.0.0.1]) by pb-smtp2.pobox.com (Postfix) with ESMTP id DA75E30FB4; Wed, 18 Sep 2024 05:15:20 -0400 (EDT) (envelope-from sakib@darkstar.site) Received: from localhost (unknown [185.130.54.100]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by pb-smtp2.pobox.com (Postfix) with ESMTPSA id AE14130FB3; Wed, 18 Sep 2024 05:15:19 -0400 (EDT) (envelope-from sakib@darkstar.site) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 87a46fe6-759e-11ef-99a2-01e77a169b0f DKIM-Signature: v=1; a=rsa-sha256; c=relaxed; d=pobox.com; h=from:to:cc :subject:date:message-id:mime-version:content-transfer-encoding; s=sasl; bh=fh9mZyzsG28FDzIQpV7iiuHkXP8frjYCraQjzlL2/QI=; b=t42u sYjjXoALLW8SBjW3CApSI92EjbVmPxNhJT+GW18prBImp6/Db6QYHSxK7w8ACmq3 S9tLm29aUlF2SxH4S1tkRTM3yDM8PiCfQRdaJArUp/75JfZr/tiS+phaZ5H59zas 8Gxua15vfuWoFcl70Vncnc+k7SZKK75/g6yOv/Q= From: Sergiy Kibrik To: xen-devel@lists.xenproject.org Cc: Sergiy Kibrik , =?utf-8?q?Roger_Pau_Monn=C3=A9?= , Stefano Stabellini , Jan Beulich , Andrew Cooper Subject: [XEN PATCH v5] x86/intel: optional build of PSR support Date: Wed, 18 Sep 2024 12:15:17 +0300 Message-Id: <20240918091517.1200080-1-Sergiy_Kibrik@epam.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 X-Pobox-Relay-ID: 86B87D34-759E-11EF-8515-9B0F950A682E-90055647!pb-smtp2.pobox.com Xen's implementation of PSR only supports Intel CPUs right now, hence it can be made dependant on CONFIG_INTEL build option. Since platform implementation is not limited to single vendor, intermediate option CONFIG_PSR introduced, which selected by CONFIG_INTEL. When !PSR then PSR-related sysctls XEN_SYSCTL_psr_cmt_op & XEN_SYSCTL_psr_alloc are off as well. Signed-off-by: Sergiy Kibrik CC: Jan Beulich CC: Andrew Cooper --- v4 patch here: https://lore.kernel.org/xen-devel/20240903072614.291048-1-Sergiy_Kibrik@epam.com/ changes in v5: - simplify psr_cmt_enabled() - move PSR config option and add description changes in v4: - introduced CONFIG_PSR - changed description - changes to psr stubs changes in v3: - drop stubs for psr_domain_{init,free} & psr_ctxt_switch_to() and guard these routines at call sites - add stub for psr_cmt_enabled() - drop some of #ifdef-s from arch_do_{domctl,sysctl} --- xen/arch/x86/Kconfig | 3 +++ xen/arch/x86/Kconfig.cpu | 1 + xen/arch/x86/Makefile | 2 +- xen/arch/x86/domctl.c | 3 +++ xen/arch/x86/include/asm/psr.h | 10 ++++++++-- xen/arch/x86/sysctl.c | 4 +++- 6 files changed, 19 insertions(+), 4 deletions(-) diff --git a/xen/arch/x86/Kconfig b/xen/arch/x86/Kconfig index 62f0b5e0f4..75d4d0bf7d 100644 --- a/xen/arch/x86/Kconfig +++ b/xen/arch/x86/Kconfig @@ -231,6 +231,9 @@ config TBOOT If unsure, stay with the default. +config PSR + bool "Platform Shared Resource support" + choice prompt "Alignment of Xen image" default XEN_ALIGN_2M if PV_SHIM_EXCLUSIVE diff --git a/xen/arch/x86/Kconfig.cpu b/xen/arch/x86/Kconfig.cpu index 5fb18db1aa..7c649a478b 100644 --- a/xen/arch/x86/Kconfig.cpu +++ b/xen/arch/x86/Kconfig.cpu @@ -13,6 +13,7 @@ config AMD config INTEL bool "Support Intel CPUs" default y + select PSR help Detection, tunings and quirks for Intel platforms. diff --git a/xen/arch/x86/Makefile b/xen/arch/x86/Makefile index 286c003ec3..4db3c214b0 100644 --- a/xen/arch/x86/Makefile +++ b/xen/arch/x86/Makefile @@ -57,7 +57,7 @@ obj-y += pci.o obj-y += percpu.o obj-y += physdev.o obj-$(CONFIG_COMPAT) += x86_64/physdev.o -obj-y += psr.o +obj-$(CONFIG_PSR) += psr.o obj-y += setup.o obj-y += shutdown.o obj-y += smp.o diff --git a/xen/arch/x86/domctl.c b/xen/arch/x86/domctl.c index 68b5b46d1a..182f5fb11b 100644 --- a/xen/arch/x86/domctl.c +++ b/xen/arch/x86/domctl.c @@ -1195,6 +1195,7 @@ long arch_do_domctl( case XEN_DOMCTL_psr_alloc: switch ( domctl->u.psr_alloc.cmd ) { +#ifdef CONFIG_PSR case XEN_DOMCTL_PSR_SET_L3_CBM: ret = psr_set_val(d, domctl->u.psr_alloc.target, domctl->u.psr_alloc.data, @@ -1257,6 +1258,8 @@ long arch_do_domctl( #undef domctl_psr_get_val +#endif /* CONFIG_PSR */ + default: ret = -EOPNOTSUPP; break; diff --git a/xen/arch/x86/include/asm/psr.h b/xen/arch/x86/include/asm/psr.h index 51df78794c..c36ce992f4 100644 --- a/xen/arch/x86/include/asm/psr.h +++ b/xen/arch/x86/include/asm/psr.h @@ -69,12 +69,11 @@ extern struct psr_cmt *psr_cmt; static inline bool psr_cmt_enabled(void) { - return !!psr_cmt; + return IS_ENABLED(CONFIG_PSR) && psr_cmt; } int psr_alloc_rmid(struct domain *d); void psr_free_rmid(struct domain *d); -void psr_ctxt_switch_to(struct domain *d); int psr_get_info(unsigned int socket, enum psr_type type, uint32_t data[], unsigned int array_len); @@ -83,8 +82,15 @@ int psr_get_val(struct domain *d, unsigned int socket, int psr_set_val(struct domain *d, unsigned int socket, uint64_t new_val, enum psr_type type); +#ifdef CONFIG_PSR +void psr_ctxt_switch_to(struct domain *d); void psr_domain_init(struct domain *d); void psr_domain_free(struct domain *d); +#else +static inline void psr_ctxt_switch_to(struct domain *d) {} +static inline void psr_domain_init(struct domain *d) {} +static inline void psr_domain_free(struct domain *d) {} +#endif #endif /* __ASM_PSR_H__ */ diff --git a/xen/arch/x86/sysctl.c b/xen/arch/x86/sysctl.c index 1d40d82c5a..fedb533ce5 100644 --- a/xen/arch/x86/sysctl.c +++ b/xen/arch/x86/sysctl.c @@ -225,10 +225,11 @@ long arch_do_sysctl( case XEN_SYSCTL_psr_alloc: { - uint32_t data[PSR_INFO_ARRAY_SIZE] = { }; + uint32_t __maybe_unused data[PSR_INFO_ARRAY_SIZE] = { }; switch ( sysctl->u.psr_alloc.cmd ) { +#ifdef CONFIG_PSR case XEN_SYSCTL_PSR_get_l3_info: ret = psr_get_info(sysctl->u.psr_alloc.target, PSR_TYPE_L3_CBM, data, ARRAY_SIZE(data)); @@ -279,6 +280,7 @@ long arch_do_sysctl( if ( __copy_field_to_guest(u_sysctl, sysctl, u.psr_alloc) ) ret = -EFAULT; break; +#endif /* CONFIG_PSR */ default: ret = -EOPNOTSUPP;