[v1,1/6] xen/arm: Decrease size of the 2nd ram bank

Commit Message

Edgar E. Iglesias Sept. 24, 2024, 4:23 p.m. UTC

From: "Edgar E. Iglesias" <[e-mail]>

The address range between 4G (32bit) and 1TB (40bit) is fully
allocated. There's no more room for devices on ARM systems with
40-bit physicall address width.

This decreases the size of the second RAM bank to free up space
in preparation for virtio-pci and for future use-cases.

In the future we may need to add a third RAM bank in higher
address ranges.

Signed-off-by: Edgar E. Iglesias <[e-mail]>
---
 xen/include/public/arch-arm.h | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

Comments

Julien Grall Sept. 24, 2024, 4:30 p.m. UTC | #1

Hi Edgar,

On 24/09/2024 17:23, Edgar E. Iglesias wrote:
> From: "Edgar E. Iglesias" <[e-mail]>
> 
> The address range between 4G (32bit) and 1TB (40bit) is fully
> allocated. There's no more room for devices on ARM systems with
> 40-bit physicall address width.
 > > This decreases the size of the second RAM bank to free up space
> in preparation for virtio-pci and for future use-cases.

I don't think we should reduce the amount of RAM supported in the 
default case. Instead, I think it is time to support a more dynamic 
layout so we still allow 1TB guest when QEMU is not emulated a virtual 
PCI hostbridge.

Cheers,

Stefano Stabellini Sept. 24, 2024, 11:34 p.m. UTC | #2

On Tue, 24 Sep 2024, Julien Grall wrote:
> Hi Edgar,
> 
> On 24/09/2024 17:23, Edgar E. Iglesias wrote:
> > From: "Edgar E. Iglesias" <[e-mail]>
> > 
> > The address range between 4G (32bit) and 1TB (40bit) is fully
> > allocated. There's no more room for devices on ARM systems with
> > 40-bit physicall address width.
> > > This decreases the size of the second RAM bank to free up space
> > in preparation for virtio-pci and for future use-cases.
> 
> I don't think we should reduce the amount of RAM supported in the default
> case. Instead, I think it is time to support a more dynamic layout so we still
> allow 1TB guest when QEMU is not emulated a virtual PCI hostbridge.

Edgar, do you think it would be possible for QEMU to take the virtio-pci
address ranges and SPIs on the command line? If yes, I think that would
solve the problem on the QEMU side.

On the Xen side, you have already added "virtio-pci-ranges" as dom0less
property and that's all we need as far as I can tell.

Then you can remove patch #1 and patch #2 from this series?

Edgar E. Iglesias Sept. 24, 2024, 11:40 p.m. UTC | #3

On Tue, Sep 24, 2024 at 04:34:16PM -0700, Stefano Stabellini wrote:
> On Tue, 24 Sep 2024, Julien Grall wrote:
> > Hi Edgar,
> > 
> > On 24/09/2024 17:23, Edgar E. Iglesias wrote:
> > > From: "Edgar E. Iglesias" <[e-mail]>
> > > 
> > > The address range between 4G (32bit) and 1TB (40bit) is fully
> > > allocated. There's no more room for devices on ARM systems with
> > > 40-bit physicall address width.
> > > > This decreases the size of the second RAM bank to free up space
> > > in preparation for virtio-pci and for future use-cases.
> > 
> > I don't think we should reduce the amount of RAM supported in the default
> > case. Instead, I think it is time to support a more dynamic layout so we still
> > allow 1TB guest when QEMU is not emulated a virtual PCI hostbridge.
> 
> Edgar, do you think it would be possible for QEMU to take the virtio-pci
> address ranges and SPIs on the command line? If yes, I think that would
> solve the problem on the QEMU side.

Yes, that is already done on the QEMU side, all addresses and sizes are
passed on the command-line.


> On the Xen side, you have already added "virtio-pci-ranges" as dom0less
> property and that's all we need as far as I can tell.
> 
> Then you can remove patch #1 and patch #2 from this series?

I didn't think of that but yes, that should actually work, good point.

Cheers,
Edgar

Patch

diff --git a/xen/include/public/arch-arm.h b/xen/include/public/arch-arm.h
index e2412a1747..e19f0251a6 100644
--- a/xen/include/public/arch-arm.h
+++ b/xen/include/public/arch-arm.h
@@ -491,8 +491,8 @@  typedef uint64_t xen_callback_t;
 #define GUEST_VPCI_PREFETCH_MEM_ADDR        xen_mk_ullong(0x100000000)
 #define GUEST_VPCI_PREFETCH_MEM_SIZE        xen_mk_ullong(0x100000000)
 
-#define GUEST_RAM1_BASE   xen_mk_ullong(0x0200000000) /* 1016GB of RAM @ 8GB */
-#define GUEST_RAM1_SIZE   xen_mk_ullong(0xfe00000000)
+#define GUEST_RAM1_BASE   xen_mk_ullong(0x0200000000) /* 952GB of RAM @ 8GB */
+#define GUEST_RAM1_SIZE   xen_mk_ullong(0xee00000000)
 
 #define GUEST_RAM_BASE    GUEST_RAM0_BASE /* Lowest RAM address */
 /* Largest amount of actual RAM, not including holes */