@@ -102,14 +102,9 @@ static int vlapic_find_highest_irr(struct vlapic *vlapic)
return vlapic_find_highest_vector(&vlapic->regs->data[APIC_IRR]);
}
-static void vlapic_error(struct vlapic *vlapic, unsigned int errmask)
+static void vlapic_error(struct vlapic *vlapic, unsigned int err_bit)
{
- unsigned long flags;
- uint32_t esr;
-
- spin_lock_irqsave(&vlapic->esr_lock, flags);
- esr = vlapic->hw.pending_esr;
- if ( (esr & errmask) != errmask )
+ if ( !test_and_set_bit(err_bit, &vlapic->hw.pending_esr) )
{
uint32_t lvterr = vlapic_get_reg(vlapic, APIC_LVTERR);
bool inj = false;
@@ -124,15 +119,12 @@ static void vlapic_error(struct vlapic *vlapic, unsigned int errmask)
if ( (lvterr & APIC_VECTOR_MASK) >= 16 )
inj = true;
else
- errmask |= APIC_ESR_RECVILL;
+ set_bit(ilog2(APIC_ESR_RECVILL), &vlapic->hw.pending_esr);
}
- vlapic->hw.pending_esr |= errmask;
-
if ( inj )
vlapic_set_irq(vlapic, lvterr & APIC_VECTOR_MASK, 0);
}
- spin_unlock_irqrestore(&vlapic->esr_lock, flags);
}
bool vlapic_test_irq(const struct vlapic *vlapic, uint8_t vec)
@@ -153,7 +145,7 @@ void vlapic_set_irq(struct vlapic *vlapic, uint8_t vec, uint8_t trig)
if ( unlikely(vec < 16) )
{
- vlapic_error(vlapic, APIC_ESR_RECVILL);
+ vlapic_error(vlapic, ilog2(APIC_ESR_RECVILL));
return;
}
@@ -525,7 +517,7 @@ void vlapic_ipi(
vlapic_domain(vlapic), vlapic, short_hand, dest, dest_mode);
if ( unlikely((icr_low & APIC_VECTOR_MASK) < 16) )
- vlapic_error(vlapic, APIC_ESR_SENDILL);
+ vlapic_error(vlapic, ilog2(APIC_ESR_SENDILL));
else if ( target )
vlapic_accept_irq(vlapic_vcpu(target), icr_low);
break;
@@ -534,7 +526,7 @@ void vlapic_ipi(
case APIC_DM_FIXED:
if ( unlikely((icr_low & APIC_VECTOR_MASK) < 16) )
{
- vlapic_error(vlapic, APIC_ESR_SENDILL);
+ vlapic_error(vlapic, ilog2(APIC_ESR_SENDILL));
break;
}
/* fall through */
@@ -803,17 +795,9 @@ void vlapic_reg_write(struct vcpu *v, unsigned int reg, uint32_t val)
break;
case APIC_ESR:
- {
- unsigned long flags;
-
- spin_lock_irqsave(&vlapic->esr_lock, flags);
- val = vlapic->hw.pending_esr;
- vlapic->hw.pending_esr = 0;
- spin_unlock_irqrestore(&vlapic->esr_lock, flags);
-
+ val = xchg(&vlapic->hw.pending_esr, 0);
vlapic_set_reg(vlapic, APIC_ESR, val);
break;
- }
case APIC_TASKPRI:
vlapic_set_reg(vlapic, APIC_TASKPRI, val & 0xff);
@@ -1716,8 +1700,6 @@ int vlapic_init(struct vcpu *v)
vlapic_reset(vlapic);
- spin_lock_init(&vlapic->esr_lock);
-
tasklet_init(&vlapic->init_sipi.tasklet, vlapic_init_sipi_action, v);
if ( v->vcpu_id == 0 )
@@ -69,7 +69,6 @@ struct vlapic {
bool hw, regs;
uint32_t id, ldr;
} loaded;
- spinlock_t esr_lock;
struct periodic_time pt;
s_time_t timer_last_update;
struct page_info *regs_page;
With vlapic->hw.pending_esr held outside of the main regs page, it's much easier to use atomic operations. Use xchg() in vlapic_reg_write(), and *set_bit() in vlapic_error(). The only interesting change is that vlapic_error() now needs to take an err_bit rather than an errmask, but thats fine for all current callers and forseable changes. No practical change. Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com> --- CC: Jan Beulich <JBeulich@suse.com> CC: Roger Pau Monné <roger.pau@citrix.com> It turns out that XSA-462 had an indentation bug in it. Our spinlock infrastructure is obscenely large. Bloat-o-meter reports: add/remove: 0/0 grow/shrink: 0/3 up/down: 0/-111 (-111) Function old new delta vlapic_init 208 190 -18 vlapic_error 112 67 -45 vlapic_reg_write 1145 1097 -48 In principle we could revert the XSA-462 patch now, and remove the LVTERR vector handling special case. MISRA is going to complain either way, because it will see the cycle through vlapic_set_irq() without considering the surrounding logic. --- xen/arch/x86/hvm/vlapic.c | 32 ++++++--------------------- xen/arch/x86/include/asm/hvm/vlapic.h | 1 - 2 files changed, 7 insertions(+), 26 deletions(-)