| Message ID | 20250201021718.699411-5-seanjc@google.com (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | x86/tsc: Try to wrangle PV clocks vs. TSC | expand |
Sean Christopherson <seanjc@google.com> writes: > Move the code to mark the TSC as reliable from sme_early_init() to > snp_secure_tsc_init(). The only reader of TSC_RELIABLE is the aptly > named check_system_tsc_reliable(), which runs in tsc_init(), i.e. > after snp_secure_tsc_init(). > > This will allow consolidating the handling of TSC_KNOWN_FREQ and > TSC_RELIABLE when overriding the TSC calibration routine. > > Cc: Nikunj A Dadhania <nikunj@amd.com> > Cc: Tom Lendacky <thomas.lendacky@amd.com> > Signed-off-by: Sean Christopherson <seanjc@google.com> Reviewed-by: Nikunj A Dadhania <nikunj@amd.com> > --- > arch/x86/coco/sev/core.c | 2 ++ > arch/x86/mm/mem_encrypt_amd.c | 3 --- > 2 files changed, 2 insertions(+), 3 deletions(-) > > diff --git a/arch/x86/coco/sev/core.c b/arch/x86/coco/sev/core.c > index 684cef70edc1..e6ce4ca72465 100644 > --- a/arch/x86/coco/sev/core.c > +++ b/arch/x86/coco/sev/core.c > @@ -3288,6 +3288,8 @@ void __init snp_secure_tsc_init(void) > return; > > setup_force_cpu_cap(X86_FEATURE_TSC_KNOWN_FREQ); > + setup_force_cpu_cap(X86_FEATURE_TSC_RELIABLE); > + > rdmsrl(MSR_AMD64_GUEST_TSC_FREQ, tsc_freq_mhz); > snp_tsc_freq_khz = (unsigned long)(tsc_freq_mhz * 1000); > > diff --git a/arch/x86/mm/mem_encrypt_amd.c b/arch/x86/mm/mem_encrypt_amd.c > index b56c5c073003..774f9677458f 100644 > --- a/arch/x86/mm/mem_encrypt_amd.c > +++ b/arch/x86/mm/mem_encrypt_amd.c > @@ -541,9 +541,6 @@ void __init sme_early_init(void) > * kernel mapped. > */ > snp_update_svsm_ca(); > - > - if (sev_status & MSR_AMD64_SNP_SECURE_TSC) > - setup_force_cpu_cap(X86_FEATURE_TSC_RELIABLE); > } > > void __init mem_encrypt_free_decrypted_mem(void) > -- > 2.48.1.362.g079036d154-goog
diff --git a/arch/x86/coco/sev/core.c b/arch/x86/coco/sev/core.c index 684cef70edc1..e6ce4ca72465 100644 --- a/arch/x86/coco/sev/core.c +++ b/arch/x86/coco/sev/core.c @@ -3288,6 +3288,8 @@ void __init snp_secure_tsc_init(void) return; setup_force_cpu_cap(X86_FEATURE_TSC_KNOWN_FREQ); + setup_force_cpu_cap(X86_FEATURE_TSC_RELIABLE); + rdmsrl(MSR_AMD64_GUEST_TSC_FREQ, tsc_freq_mhz); snp_tsc_freq_khz = (unsigned long)(tsc_freq_mhz * 1000); diff --git a/arch/x86/mm/mem_encrypt_amd.c b/arch/x86/mm/mem_encrypt_amd.c index b56c5c073003..774f9677458f 100644 --- a/arch/x86/mm/mem_encrypt_amd.c +++ b/arch/x86/mm/mem_encrypt_amd.c @@ -541,9 +541,6 @@ void __init sme_early_init(void) * kernel mapped. */ snp_update_svsm_ca(); - - if (sev_status & MSR_AMD64_SNP_SECURE_TSC) - setup_force_cpu_cap(X86_FEATURE_TSC_RELIABLE); } void __init mem_encrypt_free_decrypted_mem(void)
Move the code to mark the TSC as reliable from sme_early_init() to snp_secure_tsc_init(). The only reader of TSC_RELIABLE is the aptly named check_system_tsc_reliable(), which runs in tsc_init(), i.e. after snp_secure_tsc_init(). This will allow consolidating the handling of TSC_KNOWN_FREQ and TSC_RELIABLE when overriding the TSC calibration routine. Cc: Nikunj A Dadhania <nikunj@amd.com> Cc: Tom Lendacky <thomas.lendacky@amd.com> Signed-off-by: Sean Christopherson <seanjc@google.com> --- arch/x86/coco/sev/core.c | 2 ++ arch/x86/mm/mem_encrypt_amd.c | 3 --- 2 files changed, 2 insertions(+), 3 deletions(-)