| Message ID | 20250201021718.699411-6-seanjc@google.com (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | x86/tsc: Try to wrangle PV clocks vs. TSC | expand |
Sean Christopherson <seanjc@google.com> writes: > Move the check on having a Secure TSC to the common tsc_early_init() so > that it's obvious that having a Secure TSC is conditional, and to prepare > for adding TDX to the mix (blindly initializing *both* SNP and TDX TSC > logic looks especially weird). Agree. > > No functional change intended. > > Cc: Nikunj A Dadhania <nikunj@amd.com> > Cc: Tom Lendacky <thomas.lendacky@amd.com> > Signed-off-by: Sean Christopherson <seanjc@google.com> Reviewed-by: Nikunj A Dadhania <nikunj@amd.com> > --- > arch/x86/coco/sev/core.c | 3 --- > arch/x86/kernel/tsc.c | 3 ++- > 2 files changed, 2 insertions(+), 4 deletions(-) > > diff --git a/arch/x86/coco/sev/core.c b/arch/x86/coco/sev/core.c > index e6ce4ca72465..dab386f782ce 100644 > --- a/arch/x86/coco/sev/core.c > +++ b/arch/x86/coco/sev/core.c > @@ -3284,9 +3284,6 @@ void __init snp_secure_tsc_init(void) > { > unsigned long long tsc_freq_mhz; > > - if (!cc_platform_has(CC_ATTR_GUEST_SNP_SECURE_TSC)) > - return; > - > setup_force_cpu_cap(X86_FEATURE_TSC_KNOWN_FREQ); > setup_force_cpu_cap(X86_FEATURE_TSC_RELIABLE); > > diff --git a/arch/x86/kernel/tsc.c b/arch/x86/kernel/tsc.c > index 5a16271b7a5c..09ca0cbd4f31 100644 > --- a/arch/x86/kernel/tsc.c > +++ b/arch/x86/kernel/tsc.c > @@ -1514,7 +1514,8 @@ void __init tsc_early_init(void) > if (is_early_uv_system()) > return; > > - snp_secure_tsc_init(); > + if (cc_platform_has(CC_ATTR_GUEST_SNP_SECURE_TSC)) > + snp_secure_tsc_init(); > > if (!determine_cpu_tsc_frequencies(true)) > return; > -- > 2.48.1.362.g079036d154-goog
diff --git a/arch/x86/coco/sev/core.c b/arch/x86/coco/sev/core.c index e6ce4ca72465..dab386f782ce 100644 --- a/arch/x86/coco/sev/core.c +++ b/arch/x86/coco/sev/core.c @@ -3284,9 +3284,6 @@ void __init snp_secure_tsc_init(void) { unsigned long long tsc_freq_mhz; - if (!cc_platform_has(CC_ATTR_GUEST_SNP_SECURE_TSC)) - return; - setup_force_cpu_cap(X86_FEATURE_TSC_KNOWN_FREQ); setup_force_cpu_cap(X86_FEATURE_TSC_RELIABLE); diff --git a/arch/x86/kernel/tsc.c b/arch/x86/kernel/tsc.c index 5a16271b7a5c..09ca0cbd4f31 100644 --- a/arch/x86/kernel/tsc.c +++ b/arch/x86/kernel/tsc.c @@ -1514,7 +1514,8 @@ void __init tsc_early_init(void) if (is_early_uv_system()) return; - snp_secure_tsc_init(); + if (cc_platform_has(CC_ATTR_GUEST_SNP_SECURE_TSC)) + snp_secure_tsc_init(); if (!determine_cpu_tsc_frequencies(true)) return;
Move the check on having a Secure TSC to the common tsc_early_init() so that it's obvious that having a Secure TSC is conditional, and to prepare for adding TDX to the mix (blindly initializing *both* SNP and TDX TSC logic looks especially weird). No functional change intended. Cc: Nikunj A Dadhania <nikunj@amd.com> Cc: Tom Lendacky <thomas.lendacky@amd.com> Signed-off-by: Sean Christopherson <seanjc@google.com> --- arch/x86/coco/sev/core.c | 3 --- arch/x86/kernel/tsc.c | 3 ++- 2 files changed, 2 insertions(+), 4 deletions(-)