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pr=C From: Michal Orzel To: CC: Michal Orzel , Stefano Stabellini , Julien Grall , Bertrand Marquis , Volodymyr Babchuk Subject: [PATCH 1/2] xen/arm: Improve handling of nr_spis Date: Tue, 11 Mar 2025 10:04:08 +0100 Message-ID: <20250311090409.122577-2-michal.orzel@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250311090409.122577-1-michal.orzel@amd.com> References: <20250311090409.122577-1-michal.orzel@amd.com> MIME-Version: 1.0 Received-SPF: None (SATLEXMB04.amd.com: michal.orzel@amd.com does not designate permitted sender hosts) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ1PEPF0000231E:EE_|BL1PR12MB5851:EE_ X-MS-Office365-Filtering-Correlation-Id: 54dcec8f-d655-465e-8c0c-08dd607bb7cb X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|36860700013|82310400026|376014; X-Microsoft-Antispam-Message-Info: GDXvmGubcQy3cxVIm1WFwouJwJ3lFV74KGPtYVhF1Wsol7vvD5XOoCt5qdmg8e88jN3NDj9vSpIOdfRvLVGgbnMz0Hg4aQOFYQoflPe+t73ux0n7qWUDiKknydr8q0Kks0DG2/+nvkjXgx7NZC/2GlmXUkLvZ8mD8wRmvZr7nOE9UNmBINkpfgJrtYrzfeK8h8YJfI+zPxt8XXEK9SNGXy9UfcdB/yIdENgGBKq92JjHHkleiiCMEAf8wLkVP8NzVA+pTdFDKnmKU8RAadqgCRy0aZyZesyFZjZrInJ2wiFxB4qOuYL8YSjgRx/Avvh5Vp0toRxiFSQsDfGCwApRAOjALBPZLwbttf7unRurvPc96vmAuCpTzRqaCBmghYz4tdStruvXfKByZ76dm/vqVQ9bJ3o8JHOsRucHocJyUNcVa+NAuoScOrPaNPR0BqiUvdxc31W+i6NM4h6Zbwo8ZO+6/SDLuRnR9Fuwro2VvLEp7rBnFhlD0KhpP6H86WOHQDqgnSL4o7r+td6xoXcbwJleD0A6zZxi4aBC9eQbRHMarNzYo3qFDOiy2+9S6teHEMfMlxAsjpTVQgYSxmST6KgfVphaBfCcuYTkgvANMofM1AgWtUboWzUR6r+xIWGVugZmjEm9PoobtEGB+JSEUTrJHrfaCdR4th8a8O51JnclVlRsvgdOIBDg95PY43uCUq0DUM9fpJ+8JMgNzmcHJUVtEQ09f4Uv7yo0pxtA9PbKjpUuwL1gP41fcpRAIDswRrLDlmiWNMj12J2++4Ufic4KdRHhXMGBBcAVcU8Yl7L66OKvQrhQFQhKzbyatoHO2AmTr7AiD/QG3pFjCUhQwn0Aljn3dliMHRyucBiRuqUm1KJ6vI+RXn/+hB8aI9sWIpul3Cdt7MN//3vEzbZzAxtAwj3lSli5mUCo3rhGUkOJxCfFVmk1se0k2FWbo2n04ADaTRB4rqQrqNqiqSJxFEr82LHzHmIVd2ahJ07TGIbiE0NI3cZx94R40pHIHPxpLoP70yvQcEdFy4eYn2G3eD1FptJ5r2uINvHlAxFwxYFIGG54OQyLxEPggW7t1c+n23ZEPEfC1nOCwmjwad9bVEV/27vc1BWX0IawZ9EKhtPhG5xiMWWzuRQIM3E1uhaLUQtMHdoQJSdRjKWm6g4PJwX/yRnjmBSfciWoByHa2N92IwMSxlJjR1NJwj0qxrXM0AW9YjUcrDsK1cJKagp7KjwhpRKJu4vLHStUj9g1oVQ+f/V0JyRTOjITLwj9CbEYnRiGmhhi+GL3bIoY3291pE5mpCjFbHw4SZx4CMyMO6gBerJR5pygyxm5mjg7heNpCDR66n5MaPcvEbXXYkn/WS5l1ECNwX2NZIl/KNHIA2T7JLNLn5+hHPM77sTB1N1ZWpXTM2y8eCdWdQr9rwa62DlaDScZdR76jNjOnr2Jik/BJBizoVDNmIjhiJGQzhUkRkG4xLVbtgYVvSD7YsehrjgCGZRUKInpIQaFslTCXrY= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(1800799024)(36860700013)(82310400026)(376014);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 11 Mar 2025 09:04:23.5730 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 54dcec8f-d655-465e-8c0c-08dd607bb7cb X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF0000231E.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL1PR12MB5851 At the moment, we print a warning about max number of IRQs supported by GIC bigger than vGIC only for hardware domain. This check is not hwdom special, and should be made common. Also, in case of user not specifying nr_spis for dom0less domUs, we should take into account max number of IRQs supported by vGIC if it's smaller than for GIC. Introduce VGIC_MAX_IRQS macro and use it instead of hardcoded 992 value. Fix calculation of nr_spis for dom0less domUs and make the GIC/vGIC max IRQs comparison common. Signed-off-by: Michal Orzel --- xen/arch/arm/dom0less-build.c | 2 +- xen/arch/arm/domain_build.c | 9 ++------- xen/arch/arm/gic.c | 3 +++ xen/arch/arm/include/asm/vgic.h | 3 +++ 4 files changed, 9 insertions(+), 8 deletions(-) diff --git a/xen/arch/arm/dom0less-build.c b/xen/arch/arm/dom0less-build.c index 31f31c38da3f..9a84fee94119 100644 --- a/xen/arch/arm/dom0less-build.c +++ b/xen/arch/arm/dom0less-build.c @@ -1018,7 +1018,7 @@ void __init create_domUs(void) { int vpl011_virq = GUEST_VPL011_SPI; - d_cfg.arch.nr_spis = gic_number_lines() - 32; + d_cfg.arch.nr_spis = min(gic_number_lines(), VGIC_MAX_IRQS) - 32; /* * The VPL011 virq is GUEST_VPL011_SPI, unless direct-map is diff --git a/xen/arch/arm/domain_build.c b/xen/arch/arm/domain_build.c index 7cc141ef75e9..b99c4e3a69bf 100644 --- a/xen/arch/arm/domain_build.c +++ b/xen/arch/arm/domain_build.c @@ -2371,13 +2371,8 @@ void __init create_dom0(void) /* The vGIC for DOM0 is exactly emulating the hardware GIC */ dom0_cfg.arch.gic_version = XEN_DOMCTL_CONFIG_GIC_NATIVE; - /* - * Xen vGIC supports a maximum of 992 interrupt lines. - * 32 are substracted to cover local IRQs. - */ - dom0_cfg.arch.nr_spis = min(gic_number_lines(), (unsigned int) 992) - 32; - if ( gic_number_lines() > 992 ) - printk(XENLOG_WARNING "Maximum number of vGIC IRQs exceeded.\n"); + /* 32 are substracted to cover local IRQs */ + dom0_cfg.arch.nr_spis = min(gic_number_lines(), VGIC_MAX_IRQS) - 32; dom0_cfg.arch.tee_type = tee_get_type(); dom0_cfg.max_vcpus = dom0_max_vcpus(); diff --git a/xen/arch/arm/gic.c b/xen/arch/arm/gic.c index acf61a4de373..e80fe0ca2421 100644 --- a/xen/arch/arm/gic.c +++ b/xen/arch/arm/gic.c @@ -251,6 +251,9 @@ void __init gic_init(void) panic("Failed to initialize the GIC drivers\n"); /* Clear LR mask for cpu0 */ clear_cpu_lr_mask(); + + if ( gic_number_lines() > VGIC_MAX_IRQS ) + printk(XENLOG_WARNING "Maximum number of vGIC IRQs exceeded\n"); } void send_SGI_mask(const cpumask_t *cpumask, enum gic_sgi sgi) diff --git a/xen/arch/arm/include/asm/vgic.h b/xen/arch/arm/include/asm/vgic.h index e309dca1ad01..c549e5840bfa 100644 --- a/xen/arch/arm/include/asm/vgic.h +++ b/xen/arch/arm/include/asm/vgic.h @@ -329,6 +329,9 @@ extern void vgic_check_inflight_irqs_pending(struct vcpu *v, */ #define vgic_num_irqs(d) ((d)->arch.vgic.nr_spis + 32) +/* Maximum number of IRQs supported by vGIC */ +#define VGIC_MAX_IRQS 992U + /* * Allocate a guest VIRQ * - spi == 0 => allocate a PPI. It will be the same on every vCPU