diff --git a/xen/arch/x86/include/asm/msr.h b/xen/arch/x86/include/asm/msr.h
index 7b00a4db5d48..549d40b404cb 100644
--- a/xen/arch/x86/include/asm/msr.h
+++ b/xen/arch/x86/include/asm/msr.h
@@ -279,8 +279,6 @@ static inline void write_efer(uint64_t val)
     wrmsrl(MSR_EFER, val);
 }
 
-extern unsigned int ler_msr;
-
 DECLARE_PER_CPU(uint32_t, tsc_aux);
 
 /* Lazy update of MSR_TSC_AUX */
diff --git a/xen/arch/x86/include/asm/system.h b/xen/arch/x86/include/asm/system.h
index 73364056c702..1bf6bd026852 100644
--- a/xen/arch/x86/include/asm/system.h
+++ b/xen/arch/x86/include/asm/system.h
@@ -263,7 +263,6 @@ static inline int local_irq_is_enabled(void)
 #define BROKEN_ACPI_Sx          0x0001
 #define BROKEN_INIT_AFTER_S1    0x0002
 
-void trap_init(void);
 void init_idt_traps(void);
 void load_system_tables(void);
 void subarch_percpu_traps_init(void);
diff --git a/xen/arch/x86/include/asm/traps.h b/xen/arch/x86/include/asm/traps.h
index 825f7441c86e..3d30aa6738d4 100644
--- a/xen/arch/x86/include/asm/traps.h
+++ b/xen/arch/x86/include/asm/traps.h
@@ -7,8 +7,11 @@
 #ifndef ASM_TRAP_H
 #define ASM_TRAP_H
 
+void traps_init(void);
 void percpu_traps_init(void);
 
+extern unsigned int ler_msr;
+
 const char *vector_name(unsigned int vec);
 
 #endif /* ASM_TRAP_H */
diff --git a/xen/arch/x86/setup.c b/xen/arch/x86/setup.c
index b092106ccca5..5e2411a008f5 100644
--- a/xen/arch/x86/setup.c
+++ b/xen/arch/x86/setup.c
@@ -2023,7 +2023,7 @@ void asmlinkage __init noreturn __start_xen(void)
                                            &this_cpu(stubs).mfn);
     BUG_ON(!this_cpu(stubs.addr));
 
-    trap_init();
+    traps_init(); /* Needs stubs allocated. */
 
     cpu_init();
 
diff --git a/xen/arch/x86/traps-setup.c b/xen/arch/x86/traps-setup.c
index fa78a35a7ebf..1a7b42c14bf2 100644
--- a/xen/arch/x86/traps-setup.c
+++ b/xen/arch/x86/traps-setup.c
@@ -2,6 +2,9 @@
 /*
  * Configuration of event handling for all CPUs.
  */
+#include <xen/init.h>
+#include <xen/param.h>
+
 #include <asm/idt.h>
 #include <asm/msr.h>
 #include <asm/system.h>
@@ -9,6 +12,69 @@
 
 DEFINE_PER_CPU_READ_MOSTLY(idt_entry_t *, idt);
 
+/* LastExceptionFromIP on this hardware.  Zero if LER is not in use. */
+unsigned int __ro_after_init ler_msr;
+static bool __initdata opt_ler;
+boolean_param("ler", opt_ler);
+
+void nocall entry_PF(void);
+
+static void __init init_ler(void)
+{
+    unsigned int msr = 0;
+
+    if ( !opt_ler )
+        return;
+
+    /*
+     * Intel Pentium 4 is the only known CPU to not use the architectural MSR
+     * indicies.
+     */
+    switch ( boot_cpu_data.x86_vendor )
+    {
+    case X86_VENDOR_INTEL:
+        if ( boot_cpu_data.x86 == 0xf )
+        {
+            msr = MSR_P4_LER_FROM_LIP;
+            break;
+        }
+        fallthrough;
+    case X86_VENDOR_AMD:
+    case X86_VENDOR_HYGON:
+        msr = MSR_IA32_LASTINTFROMIP;
+        break;
+    }
+
+    if ( msr == 0 )
+    {
+        printk(XENLOG_WARNING "LER disabled: failed to identify MSRs\n");
+        return;
+    }
+
+    ler_msr = msr;
+    setup_force_cpu_cap(X86_FEATURE_XEN_LBR);
+}
+
+/*
+ * Configure complete exception, interrupt and syscall handling.
+ */
+void __init traps_init(void)
+{
+    /* Replace early pagefault with real pagefault handler. */
+    _update_gate_addr_lower(&bsp_idt[X86_EXC_PF], entry_PF);
+
+    init_ler();
+
+    /* Cache {,compat_}gdt_l1e now that physically relocation is done. */
+    this_cpu(gdt_l1e) =
+        l1e_from_pfn(virt_to_mfn(boot_gdt), __PAGE_HYPERVISOR_RW);
+    if ( IS_ENABLED(CONFIG_PV32) )
+        this_cpu(compat_gdt_l1e) =
+            l1e_from_pfn(virt_to_mfn(boot_compat_gdt), __PAGE_HYPERVISOR_RW);
+
+    percpu_traps_init();
+}
+
 /*
  * Set up per-CPU linkage registers for exception, interrupt and syscall
  * handling.
diff --git a/xen/arch/x86/traps.c b/xen/arch/x86/traps.c
index 29d7e4123f90..79d92f21acf5 100644
--- a/xen/arch/x86/traps.c
+++ b/xen/arch/x86/traps.c
@@ -107,12 +107,6 @@ DEFINE_PER_CPU_PAGE_ALIGNED(struct tss_page, tss_page);
 static int debug_stack_lines = 20;
 integer_param("debug_stack_lines", debug_stack_lines);
 
-static bool __initdata opt_ler;
-boolean_param("ler", opt_ler);
-
-/* LastExceptionFromIP on this hardware.  Zero if LER is not in use. */
-unsigned int __ro_after_init ler_msr;
-
 const unsigned int nmi_cpu;
 
 #define stack_words_per_line 4
@@ -1864,8 +1858,6 @@ void asmlinkage do_entry_CP(struct cpu_user_regs *regs)
     panic("CONTROL-FLOW PROTECTION FAULT: #CP[%04x] %s\n", ec, err);
 }
 
-void nocall entry_PF(void);
-
 void __init init_idt_traps(void)
 {
     /* Specify dedicated interrupt stacks for NMI, #DF, and #MC. */
@@ -1879,59 +1871,6 @@ void __init init_idt_traps(void)
         this_cpu(compat_gdt) = boot_compat_gdt;
 }
 
-static void __init init_ler(void)
-{
-    unsigned int msr = 0;
-
-    if ( !opt_ler )
-        return;
-
-    /*
-     * Intel Pentium 4 is the only known CPU to not use the architectural MSR
-     * indicies.
-     */
-    switch ( boot_cpu_data.x86_vendor )
-    {
-    case X86_VENDOR_INTEL:
-        if ( boot_cpu_data.x86 == 0xf )
-        {
-            msr = MSR_P4_LER_FROM_LIP;
-            break;
-        }
-        fallthrough;
-    case X86_VENDOR_AMD:
-    case X86_VENDOR_HYGON:
-        msr = MSR_IA32_LASTINTFROMIP;
-        break;
-    }
-
-    if ( msr == 0 )
-    {
-        printk(XENLOG_WARNING "LER disabled: failed to identify MSRs\n");
-        return;
-    }
-
-    ler_msr = msr;
-    setup_force_cpu_cap(X86_FEATURE_XEN_LBR);
-}
-
-void __init trap_init(void)
-{
-    /* Replace early pagefault with real pagefault handler. */
-    _update_gate_addr_lower(&bsp_idt[X86_EXC_PF], entry_PF);
-
-    init_ler();
-
-    /* Cache {,compat_}gdt_l1e now that physically relocation is done. */
-    this_cpu(gdt_l1e) =
-        l1e_from_pfn(virt_to_mfn(boot_gdt), __PAGE_HYPERVISOR_RW);
-    if ( IS_ENABLED(CONFIG_PV32) )
-        this_cpu(compat_gdt_l1e) =
-            l1e_from_pfn(virt_to_mfn(boot_compat_gdt), __PAGE_HYPERVISOR_RW);
-
-    percpu_traps_init();
-}
-
 void asm_domain_crash_synchronous(unsigned long addr)
 {
     /*
