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pr=C From: Ayan Kumar Halder To: CC: Ayan Kumar Halder , Stefano Stabellini , Julien Grall , Bertrand Marquis , Michal Orzel , "Volodymyr Babchuk" Subject: [PATCH v3 3/5] xen/arm32: Create the same boot-time MPU regions as arm64 Date: Sun, 30 Mar 2025 19:03:06 +0100 Message-ID: <20250330180308.2551195-4-ayan.kumar.halder@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250330180308.2551195-1-ayan.kumar.halder@amd.com> References: <20250330180308.2551195-1-ayan.kumar.halder@amd.com> MIME-Version: 1.0 Received-SPF: None (SATLEXMB03.amd.com: ayan.kumar.halder@amd.com does not designate permitted sender hosts) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS3PEPF000099DD:EE_|PH0PR12MB7885:EE_ X-MS-Office365-Filtering-Correlation-Id: d1873e49-90e6-44ee-9735-08dd6fb536c1 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|376014|36860700013|82310400026|34020700016; X-Microsoft-Antispam-Message-Info: qzgPoDHK6pUfDpN0FFh/WrOaih807MqfdcAlqgzQJyIO9pT41Qn0U3FHd7Eoi3G4FPe4KIm189tNYn8OP/944b2VsRhBVmbc+EgOQ8yp24TizbOzZKl/YLIYUsvWaAPHCLjpcxzGToYwchfKnuWoRFletC+gJQoM45WHWHSgmiwWIkuIx8t+Wp5Q7WNdS2myXrK+0PrrglRUQV3Zj2WVGVeNAjSneMraGkJWx/3j7xArJopNt4+8YdV1ufAkHVOvmnVWNOr6c73iHfimXG8fkhvsA+VPCTqHOK5JarsAMQQu31ggmcEn3btgBhaexZT+T5F22xOEQmEVRJKFNHLDmpXjjdNXnIbH2BgeFo6msW4AgseH2rRFVIsHwUnI24O/DcajNeomqgQhmYkESES8m6MWwxf3Zyp12mHNYMwxnW8Oz3v2bBvnR++KuCrDUoUcpRlHHUAuXqkochpPrrlc5DnRiib9ZgQ/LYSnzVFMQiXJTV7saxQ0jXL7CZFea/cW/025xTCtEqPTyXtyOMWisjgcdyRf9T6han/fwZaqhhEFZmw7p44vRamieairn+/1s8RLYHz2B1b4OqKfaYuvo3y9nggDGZhxfpHXdisd+w1Qed9ZhZ2x5ohep9q8JIKCfN+UTOt8dzUbSBjtIehRM37MsTWKdOKJ1/5qpfmaaR5GEPY0LOKqWEhcKxYK6O1/3eKdbMAMw8SFIyYmacpE5SSCdX0gu+FFhWqNAzZEEc1G8g33vh4pqb18GG2ax+/9WjGy9Jm/dxole01uYnVHP1OzuOlr0gnsOGpbJowIHxh+JuQ5OwCBy2mrXaKjwY9ffk0TxpRH+3YopS2ZaUcQxIHsD7fqFjHKQKbwcTjRB0VrCT/oVNBPaf3JnnCdgc58bwYrrxxXmWYQ2AwnwOSaixvNDFP/jIwh/+K/Ao36wEzHVGwl2DU/sS7AjjPwh8mVYDbP7ZOWMZJhu/tY9WApssIVsJhVbXtdr2TesUDdnsdi5OTYk+fw2f70H3PX2zDRIotB+ikG38Oh7oFZNnJdKZOC0Vx+ywIrRvYv+O0yuzGnBkgu+ibmSmTyGRA88G4imyXe+U9goZBze3kqx6pc1k36KxXkG/nvp5fmSliSjSxToFemLVLO5tFlnQOOOeji1dxKmlWvJPvoqTuk+k3A2O9Iar9n48Z/TOHxtOfP1gc/CgL64SWONcrQ0nH/d0XR6kSCqmliWgVDh5SAwCe/QEIKaMleJ8QomeJBDtTUv2j0luJ3onLK/AdNoauD+q857eUEY1inX7hUJjlcCVcrxP5/ygENUzWJaDykX+QiajC/GoUDf+vsm93IUfYaARzRiGp3miqXBtLjHCT0ppKclBuwBFQ/gYqwJE+0PsfHtz3qdP+jWSRCVqfU/dTdmw4U6BiSu7h/BV1F25soE2ATYz6qcAcSqV2Rv/uvzpfAenwM0/bEb+sbG5cjIYQmdBBHoCF020F6h9SWa3Ij34eRcWTiWgVzSvrGA3urQBuwVHHwG/PAD88WDFbMok27inkQ X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB03.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(1800799024)(376014)(36860700013)(82310400026)(34020700016);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Mar 2025 18:03:45.4117 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: d1873e49-90e6-44ee-9735-08dd6fb536c1 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DS3PEPF000099DD.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH0PR12MB7885 We have created the same boot-time MPU protection regions as Armv8-R AArch64. Also, we have defined REGION_* macros for arm32. The only difference from arm64 is that XN is 1-bit for arm32. The macros have been defined in arm32/sysregs.h. Though REGION_NORMAL_PRLAR and REGION_DEVICE_PRLAR are same between arm32 and arm64, we have duplicated them to keep the definitions at the same place as the other REGION_* macros. Signed-off-by: Ayan Kumar Halder --- Changes from v1 - 1. enable_mpu() now sets HMAIR{0,1} registers. This is similar to what is being done in enable_mmu(). All the mm related configurations happen in this function. 2. Fixed some typos. v2 - 1. Include the common prepare_xen_region.inc in head.S. 2. Define LOAD_SYSREG()/STORE_SYSREG() for arm32. xen/arch/arm/arm32/Makefile | 1 + xen/arch/arm/arm32/mpu/Makefile | 1 + xen/arch/arm/arm32/mpu/head.S | 52 ++++++++++++++++++++++++ xen/arch/arm/include/asm/arm32/sysregs.h | 11 +++++ xen/arch/arm/include/asm/cpregs.h | 4 ++ xen/arch/arm/include/asm/mpu/cpregs.h | 23 +++++++++++ 6 files changed, 92 insertions(+) create mode 100644 xen/arch/arm/arm32/mpu/Makefile create mode 100644 xen/arch/arm/arm32/mpu/head.S create mode 100644 xen/arch/arm/include/asm/mpu/cpregs.h diff --git a/xen/arch/arm/arm32/Makefile b/xen/arch/arm/arm32/Makefile index 40a2b4803f..537969d753 100644 --- a/xen/arch/arm/arm32/Makefile +++ b/xen/arch/arm/arm32/Makefile @@ -1,5 +1,6 @@ obj-y += lib/ obj-$(CONFIG_MMU) += mmu/ +obj-$(CONFIG_MPU) += mpu/ obj-$(CONFIG_EARLY_PRINTK) += debug.o obj-y += domctl.o diff --git a/xen/arch/arm/arm32/mpu/Makefile b/xen/arch/arm/arm32/mpu/Makefile new file mode 100644 index 0000000000..3340058c08 --- /dev/null +++ b/xen/arch/arm/arm32/mpu/Makefile @@ -0,0 +1 @@ +obj-y += head.o diff --git a/xen/arch/arm/arm32/mpu/head.S b/xen/arch/arm/arm32/mpu/head.S new file mode 100644 index 0000000000..30c901525a --- /dev/null +++ b/xen/arch/arm/arm32/mpu/head.S @@ -0,0 +1,52 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Start-of-day code for an Armv8-R MPU system. + */ + +#include +#include + +/* + * Set up the memory attribute type tables and enable EL2 MPU and data cache. + * If the Background region is enabled, then the MPU uses the default memory + * map as the Background region for generating the memory + * attributes when MPU is disabled. + * Since the default memory map of the Armv8-R AArch32 architecture is + * IMPLEMENTATION DEFINED, we intend to turn off the Background region here. + * + * Clobbers r0 - r1 + */ +FUNC_LOCAL(enable_mpu) + /* Set up memory attribute type tables */ + mov_w r0, MAIR0VAL + mov_w r1, MAIR1VAL + mcr CP32(r0, HMAIR0) + mcr CP32(r1, HMAIR1) + + mrc CP32(r0, HSCTLR) + bic r0, r0, #SCTLR_ELx_BR /* Disable Background region */ + orr r0, r0, #SCTLR_Axx_ELx_M /* Enable MPU */ + orr r0, r0, #SCTLR_Axx_ELx_C /* Enable D-cache */ + mcr CP32(r0, HSCTLR) + isb + mov pc, lr +END(enable_mpu) + +/* + * Maps the various sections of Xen (decsribed in xen.lds.S) as different MPU + * regions. + * + * Clobbers r0 - r6 + */ +FUNC(enable_boot_cpu_mm) + mov r6, lr + enable_boot_cpu r0, r1, r2, r3, r4, r5 + mov pc, r6 +END(enable_boot_cpu_mm) + +/* + * Local variables: + * mode: ASM + * indent-tabs-mode: nil + * End: + */ diff --git a/xen/arch/arm/include/asm/arm32/sysregs.h b/xen/arch/arm/include/asm/arm32/sysregs.h index 22871999af..e02c0932e6 100644 --- a/xen/arch/arm/include/asm/arm32/sysregs.h +++ b/xen/arch/arm/include/asm/arm32/sysregs.h @@ -4,6 +4,14 @@ #include #include +#define REGION_TEXT_PRBAR 0x18 /* SH=11 AP=10 XN=0 */ +#define REGION_RO_PRBAR 0x1D /* SH=11 AP=10 XN=1 */ +#define REGION_DATA_PRBAR 0x19 /* SH=11 AP=00 XN=1 */ +#define REGION_DEVICE_PRBAR 0x11 /* SH=10 AP=00 XN=1 */ + +#define REGION_NORMAL_PRLAR 0x0f /* NS=0 ATTR=111 EN=1 */ +#define REGION_DEVICE_PRLAR 0x09 /* NS=0 ATTR=100 EN=1 */ + /* Layout as used in assembly, with src/dest registers mixed in */ #define __CP32(r, coproc, opc1, crn, crm, opc2) coproc, opc1, r, crn, crm, opc2 #define __CP64(r1, r2, coproc, opc, crm) coproc, opc, r1, r2, crm @@ -16,6 +24,9 @@ #define LOAD_CP64(r, name...) "mrrc " __stringify(CP64(%r, %H##r, name)) ";" #define STORE_CP64(r, name...) "mcrr " __stringify(CP64(%r, %H##r, name)) ";" +#define LOAD_SYSREG(v, name) mrc CP32(v, name) +#define STORE_SYSREG(v, name) mcr CP32(v, name) + /* Issue a CP operation which takes no argument, * uses r0 as a placeholder register. */ #define CMD_CP32(name...) "mcr " __stringify(CP32(r0, name)) ";" diff --git a/xen/arch/arm/include/asm/cpregs.h b/xen/arch/arm/include/asm/cpregs.h index aec9e8f329..6019a2cbdd 100644 --- a/xen/arch/arm/include/asm/cpregs.h +++ b/xen/arch/arm/include/asm/cpregs.h @@ -1,6 +1,10 @@ #ifndef __ASM_ARM_CPREGS_H #define __ASM_ARM_CPREGS_H +#ifdef CONFIG_MPU +#include +#endif + /* * AArch32 Co-processor registers. * diff --git a/xen/arch/arm/include/asm/mpu/cpregs.h b/xen/arch/arm/include/asm/mpu/cpregs.h new file mode 100644 index 0000000000..cf63730233 --- /dev/null +++ b/xen/arch/arm/include/asm/mpu/cpregs.h @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __ASM_ARM_MPU_CPREGS_H +#define __ASM_ARM_MPU_CPREGS_H + +#define HMPUIR p15,4,c0,c0,4 + +/* CP15 CR6: MPU Protection Region Base/Limit/Select Address Register */ +#define HPRSELR p15,4,c6,c2,1 +#define PRBAR_EL2 p15,4,c6,c3,0 +#define PRLAR_EL2 p15,4,c6,c8,1 + +#define MPUIR_EL2 HMPUIR +#define PRSELR_EL2 HPRSELR + +#endif /* __ASM_ARM_MPU_CPREGS_H */ + +/* + * Local variables: + * mode: ASM + * indent-tabs-mode: nil + * End: + */