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pr=C From: Ayan Kumar Halder To: CC: Ayan Kumar Halder , Stefano Stabellini , Julien Grall , Bertrand Marquis , Michal Orzel , "Volodymyr Babchuk" , Luca Fancellu Subject: [PATCH v7 1/3] xen/arm: Move some of the functions to common file Date: Mon, 14 Apr 2025 17:45:12 +0100 Message-ID: <20250414164514.588373-2-ayan.kumar.halder@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250414164514.588373-1-ayan.kumar.halder@amd.com> References: <20250414164514.588373-1-ayan.kumar.halder@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ1PEPF00001CEB:EE_|SA1PR12MB9492:EE_ X-MS-Office365-Filtering-Correlation-Id: 04d68a0e-0f7c-4593-952b-08dd7b73c771 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|36860700013|376014|1800799024; X-Microsoft-Antispam-Message-Info: uf8G5axzb8Wg51YjAODCrwi2/Aw3FNdB95akj5W+qqRVFaMSUvz+F2wo/SFkE1uqcduvJeQD6YNhKpq4H3IIhGlw6GmgdQg1lohjNxQk+IyBiM/9XnUdJNQi2rt5eZtWn3hGD4wOP4yUS8uPo2kR1aUnDdKVeobYxOGkh4Fallr/Xg3YSnbR23YmYhGmWnK/TjZT83v2yfShX8hXWGPrkMo8pN3ccMY+3oFAI6IG7NePIAKrEwaH2X/VfPlFY2PcVShLbXmbAqtNNRA9KPORJXhZVCVOvbOsGOBh3ejbLmyip3PL9kYo8j4H5Yf4MXyOs2nC85Vh0VmU+U/OL+ioCgugs/McTXxYgTdxHkd2w5WtlGFRMRuGDKB/rfLhV99WWTZK6aXw4D50DI5auW1IVJzim/5pxHc2vvEIFpWufJFA7Tirgkrj9Op2/eHfzRUwCwG4ZiGHpjg4QeBcSIYK3sFsokNRUvix9cjs2C1M/Jm3Ak39m4LIQTX9jD7K3IgS6pOdi4cQmzgR8PCvD3I2OQ5YEbwgxqxVj/qDQCGwxsXE2VZ9he9kEjgLNeuc1BJQhcnJP+aB1eyvhoKhgyXaiCccFoyDtvc9D4F3u2JUoSfhBmwAHFu8sHzbUJ/3AGcJB51dUqQW1g4Zsn63VosmlIc7dXQVRCNcxnSfVW88KRNZtPg+nMRxtMpnP3jtFTV+DveNjIgn31nz2WB7Iahpp8IFUpoiRLGPy+8Jk6bLbVDcTY/34bWDdv+up6VhbEFRdHi9O6lWpXLV9SBuGQ6hF8M76pSs3/W0XA6/0iVQ3AdON28xdy67uOO0QsBYCOtmYBD0tLdf+FCEBXJtZP2zOcXSM5BIWppp8DnxbNeamqLktLteubllflUxDWCLQ1R0w+cwyZ07TyUq9X0mvwfXrtIXAMYLq3zTmPcchaQoMdyLeVS8UlrJUhiLCEiEvo2/4A9hIKRPOkDTFUkxQH2z7ug62yPmBRTXMLepeotu6y1O67+bSFilR76YCrxsKhek4hPdFHDYbSLnkG+Bynf90ScIKom/pWmf/ai5XYctoLrawtetYQYrTr+EenAKKE963Qs+JwgxMLuv2vyB63zQvamxgKx/KDK5t01pxMGs0wZYlhmFoiLfjYNDLpmIj9FMh+4+QmMasuQo/gmHO1DI81xh2qVpEScgMOXfh0L6r8U0xp2vHshhwByFyFcwm/folBatgQF3Ygb40ywib5jwRHpS0D8QtmvCcXZEh7/qwksQMLZSywtml+A+GGnpKuGcXBT5j1LVsLh8Gu/wHmb+nU3UHtUA2L4zPrYvNS6AE8tWMm/0Hfk74odulF5Ksy+sbos+4kN9f1sfPGQMnFpRVclpJ4alM5tsqwb3jO4WwTf7NzUuEN8c1K7iOR5B9cMh1Dsu6os0Ca7SRjRng9PTaRavD9vlcyqwFrnx+Hnp89U7AklrFSjvKPPHSJqrS2SsglK2F4SUMMfMSsDtgnrNsl8ZtzZO0Ov25zUYSXbCZ977WfFLAgjosjpvnCc7Qz0k X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB03.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(82310400026)(36860700013)(376014)(1800799024);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 14 Apr 2025 16:45:35.2637 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 04d68a0e-0f7c-4593-952b-08dd7b73c771 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF00001CEB.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA1PR12MB9492 regions.inc is added to hold the common earlyboot MPU regions configurations between arm64 and arm32. prepare_xen_region, fail_insufficient_regions() will be used by both arm32 and arm64. Thus, they have been moved to regions.inc. *_PRBAR are moved to arm64/sysregs.h. *_PRLAR are moved to regions.inc as they are common between arm32 and arm64. Introduce WRITE_SYSREG_ASM to write to the system registers from regions.inc. Signed-off-by: Ayan Kumar Halder Reviewed-by: Luca Fancellu Reviewed-by: Michal Orzel Tested-by: Luca Fancellu --- Changes from v1 - 1. enable_mpu() now sets HMAIR{0,1} registers. This is similar to what is being done in enable_mmu(). All the mm related configurations happen in this function. 2. Fixed some typos. v2 - 1. Extracted the arm64 head.S functions/macros in a common file. v3 - 1. Moved *_PRLAR are moved to prepare_xen_region.inc 2. enable_boot_cpu_mm() is preserved in mpu/head.S. 3. STORE_SYSREG is renamed as WRITE_SYSREG_ASM() 4. LOAD_SYSREG is removed. 5. No need to save/restore lr in enable_boot_cpu_mm(). IOW, keep it as it was in the original code. v4 - 1. Rename prepare_xen_region.inc to common.inc 2. enable_secondary_cpu_mm() is moved back to mpu/head.S. v5 - 1. Rename common.inc to regions.inc. 2. WRITE_SYSREG_ASM() in enclosed within #ifdef __ASSEMBLY__. v6 - 1. Add Michal's R-b and Luca's T-b. xen/arch/arm/arm64/mpu/head.S | 78 +---------------------- xen/arch/arm/include/asm/arm64/sysregs.h | 13 ++++ xen/arch/arm/include/asm/mpu/regions.inc | 79 ++++++++++++++++++++++++ 3 files changed, 93 insertions(+), 77 deletions(-) create mode 100644 xen/arch/arm/include/asm/mpu/regions.inc diff --git a/xen/arch/arm/arm64/mpu/head.S b/xen/arch/arm/arm64/mpu/head.S index ed01993d85..6d336cafbb 100644 --- a/xen/arch/arm/arm64/mpu/head.S +++ b/xen/arch/arm/arm64/mpu/head.S @@ -3,83 +3,7 @@ * Start-of-day code for an Armv8-R MPU system. */ -#include -#include - -/* Backgroud region enable/disable */ -#define SCTLR_ELx_BR BIT(17, UL) - -#define REGION_TEXT_PRBAR 0x38 /* SH=11 AP=10 XN=00 */ -#define REGION_RO_PRBAR 0x3A /* SH=11 AP=10 XN=10 */ -#define REGION_DATA_PRBAR 0x32 /* SH=11 AP=00 XN=10 */ -#define REGION_DEVICE_PRBAR 0x22 /* SH=10 AP=00 XN=10 */ - -#define REGION_NORMAL_PRLAR 0x0f /* NS=0 ATTR=111 EN=1 */ -#define REGION_DEVICE_PRLAR 0x09 /* NS=0 ATTR=100 EN=1 */ - -/* - * Macro to prepare and set a EL2 MPU memory region. - * We will also create an according MPU memory region entry, which - * is a structure of pr_t, in table \prmap. - * - * sel: region selector - * base: reg storing base address - * limit: reg storing limit address - * prbar: store computed PRBAR_EL2 value - * prlar: store computed PRLAR_EL2 value - * maxcount: maximum number of EL2 regions supported - * attr_prbar: PRBAR_EL2-related memory attributes. If not specified it will be - * REGION_DATA_PRBAR - * attr_prlar: PRLAR_EL2-related memory attributes. If not specified it will be - * REGION_NORMAL_PRLAR - * - * Preserves \maxcount - * Output: - * \sel: Next available region selector index. - * Clobbers \base, \limit, \prbar, \prlar - * - * Note that all parameters using registers should be distinct. - */ -.macro prepare_xen_region, sel, base, limit, prbar, prlar, maxcount, attr_prbar=REGION_DATA_PRBAR, attr_prlar=REGION_NORMAL_PRLAR - /* Check if the region is empty */ - cmp \base, \limit - beq 1f - - /* Check if the number of regions exceeded the count specified in MPUIR_EL2 */ - cmp \sel, \maxcount - bge fail_insufficient_regions - - /* Prepare value for PRBAR_EL2 reg and preserve it in \prbar.*/ - and \base, \base, #MPU_REGION_MASK - mov \prbar, #\attr_prbar - orr \prbar, \prbar, \base - - /* Limit address should be inclusive */ - sub \limit, \limit, #1 - and \limit, \limit, #MPU_REGION_MASK - mov \prlar, #\attr_prlar - orr \prlar, \prlar, \limit - - msr PRSELR_EL2, \sel - isb - msr PRBAR_EL2, \prbar - msr PRLAR_EL2, \prlar - dsb sy - isb - - add \sel, \sel, #1 - -1: -.endm - -/* - * Failure caused due to insufficient MPU regions. - */ -FUNC_LOCAL(fail_insufficient_regions) - PRINT("- Selected MPU region is above the implemented number in MPUIR_EL2 -\r\n") -1: wfe - b 1b -END(fail_insufficient_regions) +#include /* * Enable EL2 MPU and data cache diff --git a/xen/arch/arm/include/asm/arm64/sysregs.h b/xen/arch/arm/include/asm/arm64/sysregs.h index b593e4028b..7440d495e4 100644 --- a/xen/arch/arm/include/asm/arm64/sysregs.h +++ b/xen/arch/arm/include/asm/arm64/sysregs.h @@ -462,6 +462,17 @@ #define ZCR_ELx_LEN_SIZE 9 #define ZCR_ELx_LEN_MASK 0x1ff +#define REGION_TEXT_PRBAR 0x38 /* SH=11 AP=10 XN=00 */ +#define REGION_RO_PRBAR 0x3A /* SH=11 AP=10 XN=10 */ +#define REGION_DATA_PRBAR 0x32 /* SH=11 AP=00 XN=10 */ +#define REGION_DEVICE_PRBAR 0x22 /* SH=10 AP=00 XN=10 */ + +#ifdef __ASSEMBLY__ + +#define WRITE_SYSREG_ASM(v, name) "msr " __stringify(name,) #v + +#else /* __ASSEMBLY__ */ + /* Access to system registers */ #define WRITE_SYSREG64(v, name) do { \ @@ -481,6 +492,8 @@ #define WRITE_SYSREG_LR(v, index) WRITE_SYSREG(v, ICH_LR_REG(index)) #define READ_SYSREG_LR(index) READ_SYSREG(ICH_LR_REG(index)) +#endif /* !__ASSEMBLY__ */ + #endif /* _ASM_ARM_ARM64_SYSREGS_H */ /* diff --git a/xen/arch/arm/include/asm/mpu/regions.inc b/xen/arch/arm/include/asm/mpu/regions.inc new file mode 100644 index 0000000000..47868a1526 --- /dev/null +++ b/xen/arch/arm/include/asm/mpu/regions.inc @@ -0,0 +1,79 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include + +/* Backgroud region enable/disable */ +#define SCTLR_ELx_BR BIT(17, UL) + +#define REGION_NORMAL_PRLAR 0x0f /* NS=0 ATTR=111 EN=1 */ +#define REGION_DEVICE_PRLAR 0x09 /* NS=0 ATTR=100 EN=1 */ + +/* + * Macro to prepare and set a EL2 MPU memory region. + * We will also create an according MPU memory region entry, which + * is a structure of pr_t, in table \prmap. + * + * sel: region selector + * base: reg storing base address + * limit: reg storing limit address + * prbar: store computed PRBAR_EL2 value + * prlar: store computed PRLAR_EL2 value + * maxcount: maximum number of EL2 regions supported + * attr_prbar: PRBAR_EL2-related memory attributes. If not specified it will be + * REGION_DATA_PRBAR + * attr_prlar: PRLAR_EL2-related memory attributes. If not specified it will be + * REGION_NORMAL_PRLAR + * + * Preserves maxcount + * Output: + * sel: Next available region selector index. + * Clobbers base, limit, prbar, prlar + * + * Note that all parameters using registers should be distinct. + */ +.macro prepare_xen_region, sel, base, limit, prbar, prlar, maxcount, attr_prbar=REGION_DATA_PRBAR, attr_prlar=REGION_NORMAL_PRLAR + /* Check if the region is empty */ + cmp \base, \limit + beq 1f + + /* Check if the number of regions exceeded the count specified in MPUIR_EL2 */ + cmp \sel, \maxcount + bge fail_insufficient_regions + + /* Prepare value for PRBAR_EL2 reg and preserve it in \prbar.*/ + and \base, \base, #MPU_REGION_MASK + mov \prbar, #\attr_prbar + orr \prbar, \prbar, \base + + /* Limit address should be inclusive */ + sub \limit, \limit, #1 + and \limit, \limit, #MPU_REGION_MASK + mov \prlar, #\attr_prlar + orr \prlar, \prlar, \limit + + WRITE_SYSREG_ASM(\sel, PRSELR_EL2) + isb + WRITE_SYSREG_ASM(\prbar, PRBAR_EL2) + WRITE_SYSREG_ASM(\prlar, PRLAR_EL2) + dsb sy + isb + + add \sel, \sel, #1 + +1: +.endm + +/* Failure caused due to insufficient MPU regions. */ +FUNC_LOCAL(fail_insufficient_regions) + PRINT("- Selected MPU region is above the implemented number in MPUIR_EL2 -\r\n") +1: wfe + b 1b +END(fail_insufficient_regions) + +/* + * Local variables: + * mode: ASM + * indent-tabs-mode: nil + * End: + */