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banners=-,-,- X-VirusChecked: Checked Received: (qmail 14891 invoked from network); 13 Oct 2016 13:27:05 -0000 Received: from smtp.eu.citrix.com (HELO SMTP.EU.CITRIX.COM) (185.25.65.24) by server-13.tower-31.messagelabs.com with RC4-SHA encrypted SMTP; 13 Oct 2016 13:27:05 -0000 X-IronPort-AV: E=Sophos;i="5.31,339,1473120000"; d="scan'208";a="32986552" To: Jan Beulich , xen-devel References: <57FFA0C60200007800117173@prv-mh.provo.novell.com> From: Andrew Cooper Message-ID: <22302ebd-ea41-afd8-cc5d-fb209786ba4c@citrix.com> Date: Thu, 13 Oct 2016 14:26:35 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:45.0) Gecko/20100101 Icedove/45.4.0 MIME-Version: 1.0 In-Reply-To: <57FFA0C60200007800117173@prv-mh.provo.novell.com> X-ClientProxiedBy: AMSPEX02CAS01.citrite.net (10.69.22.112) To AMSPEX02CL02.citrite.net (10.69.22.126) X-DLP: AMS1 Subject: Re: [Xen-devel] [PATCH] x86emul: honor MXCSR.MM X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xen.org Sender: "Xen-devel" X-Virus-Scanned: ClamAV using ClamSMTP On 13/10/16 13:57, Jan Beulich wrote: > Commit 6dc9ac9f52 ("x86emul: check alignment of SSE and AVX memory > operands") didn't consider a specific AMD mode: Mis-alignment #GP > faults can be masked on some of their hardware. > > Signed-off-by: Jan Beulich This highlights that the following CPUID dependency change is also required before # SSE, which is why they behave differently based on %CR4.OSFXSAVE and > > --- a/xen/arch/x86/x86_emulate/x86_emulate.c > +++ b/xen/arch/x86/x86_emulate/x86_emulate.c > @@ -446,6 +446,9 @@ typedef union { > #define EFLG_PF (1<<2) > #define EFLG_CF (1<<0) > > +/* MXCSR bit definitions. */ > +#define MXCSR_MM (1U << 17) > + > /* Exception definitions. */ > #define EXC_DE 0 > #define EXC_DB 1 > @@ -1253,6 +1256,7 @@ static bool_t vcpu_has( > > #define vcpu_has_clflush() vcpu_has( 1, EDX, 19, ctxt, ops) > #define vcpu_has_lzcnt() vcpu_has(0x80000001, ECX, 5, ctxt, ops) > +#define vcpu_has_misalignsse() vcpu_has(0x80000001, ECX, 7, ctxt, ops) > #define vcpu_has_bmi1() vcpu_has(0x00000007, EBX, 3, ctxt, ops) > #define vcpu_has_hle() vcpu_has(0x00000007, EBX, 4, ctxt, ops) > #define vcpu_has_rtm() vcpu_has(0x00000007, EBX, 11, ctxt, ops) > @@ -4675,7 +4679,13 @@ x86_emulate( > ea.bytes = vex.pfx & VEX_PREFIX_DOUBLE_MASK ? 8 : 4; > if ( ea.type == OP_MEM ) > { > - generate_exception_if((b >= 0x28) && > + uint32_t mxcsr = 0; > + > + if ( b < 0x28 ) > + mxcsr = MXCSR_MM; > + else if ( vcpu_has_misalignsse() ) > + asm ( "stmxcsr %0" : "=m" (mxcsr) ); > + generate_exception_if(!(mxcsr & MXCSR_MM) && > !is_aligned(ea.mem.seg, ea.mem.off, ea.bytes, > ctxt, ops), > EXC_GP, 0); > @@ -4955,7 +4965,13 @@ x86_emulate( > } > if ( ea.type == OP_MEM ) > { > - generate_exception_if((vex.pfx == vex_66) && > + uint32_t mxcsr = 0; > + > + if ( vex.pfx != vex_66 ) > + mxcsr = MXCSR_MM; > + else if ( vcpu_has_misalignsse() ) > + asm ( "stmxcsr %0" : "=m" (mxcsr) ); > + generate_exception_if(!(mxcsr & MXCSR_MM) && > !is_aligned(ea.mem.seg, ea.mem.off, ea.bytes, > ctxt, ops), > EXC_GP, 0); According to the docs, we should also be possibly raising #AC here. ~Andrew Reviewed-by: Andrew Cooper diff --git a/xen/tools/gen-cpuid.py b/xen/tools/gen-cpuid.py index 33e68eb..e803654 100755 --- a/xen/tools/gen-cpuid.py +++ b/xen/tools/gen-cpuid.py @@ -185,8 +185,9 @@ def crunch_numbers(state): # the first place. APIC: [X2APIC], - # AMD built MMXExtentions and 3DNow as extentions to MMX. - MMX: [MMXEXT, _3DNOW], + # AMD built MMXExtentions, 3DNow and SSE Misalignment as extensions to + # MMX. + MMX: [MMXEXT, _3DNOW, MISALIGNSSE], # The FXSAVE/FXRSTOR instructions were introduced into hardware