| Message ID | 248b4ea259aa78a17b7b05043ed211a00863bf94.1724247366.git.matthew.barnes@cloud.com (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | [v2] x86/cpufeatures: Add new cpuid features in SPR to featureset | expand |
On 21.08.2024 17:34, Matthew Barnes wrote: > Upon running `xen-cpuid -v` on a host machine with Sapphire Rapids > within Dom0, there exist unrecognised features. > > This patch adds these features as macros to the CPU featureset, > disabled by default. > > Signed-off-by: Matthew Barnes <matthew.barnes@cloud.com> I don't strictly mind the patch in this shape, but ... > @@ -276,10 +283,13 @@ XEN_CPUFEATURE(TSX_FORCE_ABORT, 9*32+13) /* MSR_TSX_FORCE_ABORT.RTM_ABORT */ > XEN_CPUFEATURE(SERIALIZE, 9*32+14) /*A SERIALIZE insn */ > XEN_CPUFEATURE(HYBRID, 9*32+15) /* Heterogeneous platform */ > XEN_CPUFEATURE(TSXLDTRK, 9*32+16) /*a TSX load tracking suspend/resume insns */ > +XEN_CPUFEATURE(PCONFIG, 9*32+18) /* PCONFIG insn */ > XEN_CPUFEATURE(ARCH_LBR, 9*32+19) /* Architectural Last Branch Record */ > XEN_CPUFEATURE(CET_IBT, 9*32+20) /* CET - Indirect Branch Tracking */ > +XEN_CPUFEATURE(AMX_BF16, 9*32+22) /* Tile computational operations on bfloat16 numbers */ > XEN_CPUFEATURE(AVX512_FP16, 9*32+23) /*A AVX512 FP16 instructions */ > XEN_CPUFEATURE(AMX_TILE, 9*32+24) /* AMX Tile architecture */ > +XEN_CPUFEATURE(AMX_INT8, 9*32+25) /* Tile computational operations on 8-bit integers */ > XEN_CPUFEATURE(IBRSB, 9*32+26) /*A IBRS and IBPB support (used by Intel) */ > XEN_CPUFEATURE(STIBP, 9*32+27) /*A STIBP */ > XEN_CPUFEATURE(L1D_FLUSH, 9*32+28) /*S MSR_FLUSH_CMD and L1D flush. */ ... having had a respective (more complete) patch pending for years I really wonder if it shouldn't be that one to be taken. While it would need adjustment to go ahead of other stuff (as posted in v3), I don't think it has any true dependency on earlier patches in the AMX series. IOW I could re-post v4 standalone, and then we'd have a more complete view on AMX as well as proper dependencies in place. Thoughts? Jan
On Wed Aug 21, 2024 at 5:07 PM BST, Jan Beulich wrote: > On 21.08.2024 17:34, Matthew Barnes wrote: > > Upon running `xen-cpuid -v` on a host machine with Sapphire Rapids > > within Dom0, there exist unrecognised features. > > > > This patch adds these features as macros to the CPU featureset, > > disabled by default. > > > > Signed-off-by: Matthew Barnes <matthew.barnes@cloud.com> > > I don't strictly mind the patch in this shape, but ... > > > @@ -276,10 +283,13 @@ XEN_CPUFEATURE(TSX_FORCE_ABORT, 9*32+13) /* MSR_TSX_FORCE_ABORT.RTM_ABORT */ > > XEN_CPUFEATURE(SERIALIZE, 9*32+14) /*A SERIALIZE insn */ > > XEN_CPUFEATURE(HYBRID, 9*32+15) /* Heterogeneous platform */ > > XEN_CPUFEATURE(TSXLDTRK, 9*32+16) /*a TSX load tracking suspend/resume insns */ > > +XEN_CPUFEATURE(PCONFIG, 9*32+18) /* PCONFIG insn */ > > XEN_CPUFEATURE(ARCH_LBR, 9*32+19) /* Architectural Last Branch Record */ > > XEN_CPUFEATURE(CET_IBT, 9*32+20) /* CET - Indirect Branch Tracking */ > > +XEN_CPUFEATURE(AMX_BF16, 9*32+22) /* Tile computational operations on bfloat16 numbers */ > > XEN_CPUFEATURE(AVX512_FP16, 9*32+23) /*A AVX512 FP16 instructions */ > > XEN_CPUFEATURE(AMX_TILE, 9*32+24) /* AMX Tile architecture */ > > +XEN_CPUFEATURE(AMX_INT8, 9*32+25) /* Tile computational operations on 8-bit integers */ > > XEN_CPUFEATURE(IBRSB, 9*32+26) /*A IBRS and IBPB support (used by Intel) */ > > XEN_CPUFEATURE(STIBP, 9*32+27) /*A STIBP */ > > XEN_CPUFEATURE(L1D_FLUSH, 9*32+28) /*S MSR_FLUSH_CMD and L1D flush. */ > > ... having had a respective (more complete) patch pending for years I really > wonder if it shouldn't be that one to be taken. While it would need adjustment > to go ahead of other stuff (as posted in v3), I don't think it has any true > dependency on earlier patches in the AMX series. IOW I could re-post v4 > standalone, and then we'd have a more complete view on AMX as well as proper > dependencies in place. > > Thoughts? > > Jan Oh! I had no idea you already posted patches to enable AMX. Is this the one? https://lore.kernel.org/xen-devel/322de6db-e01f-0b57-5777-5d94a13c441a@suse.com/ Cheers, Alejandro
On 02.09.2024 10:46, Alejandro Vallejo wrote: > On Wed Aug 21, 2024 at 5:07 PM BST, Jan Beulich wrote: >> On 21.08.2024 17:34, Matthew Barnes wrote: >>> Upon running `xen-cpuid -v` on a host machine with Sapphire Rapids >>> within Dom0, there exist unrecognised features. >>> >>> This patch adds these features as macros to the CPU featureset, >>> disabled by default. >>> >>> Signed-off-by: Matthew Barnes <matthew.barnes@cloud.com> >> >> I don't strictly mind the patch in this shape, but ... >> >>> @@ -276,10 +283,13 @@ XEN_CPUFEATURE(TSX_FORCE_ABORT, 9*32+13) /* MSR_TSX_FORCE_ABORT.RTM_ABORT */ >>> XEN_CPUFEATURE(SERIALIZE, 9*32+14) /*A SERIALIZE insn */ >>> XEN_CPUFEATURE(HYBRID, 9*32+15) /* Heterogeneous platform */ >>> XEN_CPUFEATURE(TSXLDTRK, 9*32+16) /*a TSX load tracking suspend/resume insns */ >>> +XEN_CPUFEATURE(PCONFIG, 9*32+18) /* PCONFIG insn */ >>> XEN_CPUFEATURE(ARCH_LBR, 9*32+19) /* Architectural Last Branch Record */ >>> XEN_CPUFEATURE(CET_IBT, 9*32+20) /* CET - Indirect Branch Tracking */ >>> +XEN_CPUFEATURE(AMX_BF16, 9*32+22) /* Tile computational operations on bfloat16 numbers */ >>> XEN_CPUFEATURE(AVX512_FP16, 9*32+23) /*A AVX512 FP16 instructions */ >>> XEN_CPUFEATURE(AMX_TILE, 9*32+24) /* AMX Tile architecture */ >>> +XEN_CPUFEATURE(AMX_INT8, 9*32+25) /* Tile computational operations on 8-bit integers */ >>> XEN_CPUFEATURE(IBRSB, 9*32+26) /*A IBRS and IBPB support (used by Intel) */ >>> XEN_CPUFEATURE(STIBP, 9*32+27) /*A STIBP */ >>> XEN_CPUFEATURE(L1D_FLUSH, 9*32+28) /*S MSR_FLUSH_CMD and L1D flush. */ >> >> ... having had a respective (more complete) patch pending for years I really >> wonder if it shouldn't be that one to be taken. While it would need adjustment >> to go ahead of other stuff (as posted in v3), I don't think it has any true >> dependency on earlier patches in the AMX series. IOW I could re-post v4 >> standalone, and then we'd have a more complete view on AMX as well as proper >> dependencies in place. >> >> Thoughts? >> >> Jan > > Oh! I had no idea you already posted patches to enable AMX. Is this the one? > > https://lore.kernel.org/xen-devel/322de6db-e01f-0b57-5777-5d94a13c441a@suse.com/ Yes. And specifically patch 9 there for the purposes here, suitably re-based of course and extended to cover AMX-FP16 and AMX-COMPLEX. Jan
On 21/08/2024 4:34 pm, Matthew Barnes wrote: > Upon running `xen-cpuid -v` on a host machine with Sapphire Rapids > within Dom0, there exist unrecognised features. > > This patch adds these features as macros to the CPU featureset, > disabled by default. > > Signed-off-by: Matthew Barnes <matthew.barnes@cloud.com> Acked-by: Andrew Cooper <andrew.cooper3@citrix.com> I've rebased this over Jan's AMX adjustments. ~Andrew
diff --git a/xen/include/public/arch-x86/cpufeatureset.h b/xen/include/public/arch-x86/cpufeatureset.h index abab78fa86db..9daaf92988ed 100644 --- a/xen/include/public/arch-x86/cpufeatureset.h +++ b/xen/include/public/arch-x86/cpufeatureset.h @@ -121,6 +121,7 @@ XEN_CPUFEATURE(SMX, 1*32+ 6) /* Safer Mode Extensions */ XEN_CPUFEATURE(EIST, 1*32+ 7) /* Enhanced SpeedStep */ XEN_CPUFEATURE(TM2, 1*32+ 8) /* Thermal Monitor 2 */ XEN_CPUFEATURE(SSSE3, 1*32+ 9) /*A Supplemental Streaming SIMD Extensions-3 */ +XEN_CPUFEATURE(SDBG, 1*32+11) /* IA32_DEBUG_INTERFACE MSR for silicon debugging support */ XEN_CPUFEATURE(FMA, 1*32+12) /*A Fused Multiply Add */ XEN_CPUFEATURE(CX16, 1*32+13) /*A CMPXCHG16B */ XEN_CPUFEATURE(XTPR, 1*32+14) /* Send Task Priority Messages */ @@ -181,6 +182,7 @@ XEN_CPUFEATURE(XSAVEOPT, 4*32+ 0) /*A XSAVEOPT instruction */ XEN_CPUFEATURE(XSAVEC, 4*32+ 1) /*A XSAVEC/XRSTORC instructions */ XEN_CPUFEATURE(XGETBV1, 4*32+ 2) /*A XGETBV with %ecx=1 */ XEN_CPUFEATURE(XSAVES, 4*32+ 3) /*S XSAVES/XRSTORS instructions */ +XEN_CPUFEATURE(XFD, 4*32+ 4) /* MSR_XFD{,_ERR} (eXtended Feature Disable) */ /* Intel-defined CPU features, CPUID level 0x00000007:0.ebx, word 5 */ XEN_CPUFEATURE(FSGSBASE, 5*32+ 0) /*A {RD,WR}{FS,GS}BASE instructions */ @@ -221,6 +223,7 @@ XEN_CPUFEATURE(AVX512_VBMI, 6*32+ 1) /*A AVX-512 Vector Byte Manipulation Ins XEN_CPUFEATURE(UMIP, 6*32+ 2) /*S User Mode Instruction Prevention */ XEN_CPUFEATURE(PKU, 6*32+ 3) /*H Protection Keys for Userspace */ XEN_CPUFEATURE(OSPKE, 6*32+ 4) /*! OS Protection Keys Enable */ +XEN_CPUFEATURE(WAITPKG, 6*32+ 5) /* UMONITOR/UMWAIT/TPAUSE monitoring support */ XEN_CPUFEATURE(AVX512_VBMI2, 6*32+ 6) /*A Additional AVX-512 Vector Byte Manipulation Instrs */ XEN_CPUFEATURE(CET_SS, 6*32+ 7) /* CET - Shadow Stacks */ XEN_CPUFEATURE(GFNI, 6*32+ 8) /*A Galois Field Instrs */ @@ -228,13 +231,16 @@ XEN_CPUFEATURE(VAES, 6*32+ 9) /*A Vector AES Instrs */ XEN_CPUFEATURE(VPCLMULQDQ, 6*32+10) /*A Vector Carry-less Multiplication Instrs */ XEN_CPUFEATURE(AVX512_VNNI, 6*32+11) /*A Vector Neural Network Instrs */ XEN_CPUFEATURE(AVX512_BITALG, 6*32+12) /*A Support for VPOPCNT[B,W] and VPSHUFBITQMB */ +XEN_CPUFEATURE(TME, 6*32+13) /* Total Memory Encryption */ XEN_CPUFEATURE(AVX512_VPOPCNTDQ, 6*32+14) /*A POPCNT for vectors of DW/QW */ +XEN_CPUFEATURE(LA57, 6*32+16) /* 5-level paging (57-bit linear address) */ XEN_CPUFEATURE(RDPID, 6*32+22) /*A RDPID instruction */ XEN_CPUFEATURE(BLD, 6*32+24) /* BusLock Detect (#DB trap) support */ XEN_CPUFEATURE(CLDEMOTE, 6*32+25) /*A CLDEMOTE instruction */ XEN_CPUFEATURE(MOVDIRI, 6*32+27) /*a MOVDIRI instruction */ XEN_CPUFEATURE(MOVDIR64B, 6*32+28) /*a MOVDIR64B instruction */ XEN_CPUFEATURE(ENQCMD, 6*32+29) /* ENQCMD{,S} instructions */ +XEN_CPUFEATURE(SGX_LC, 6*32+30) /* SGX Launch Configuration */ XEN_CPUFEATURE(PKS, 6*32+31) /*H Protection Key for Supervisor */ /* AMD-defined CPU features, CPUID level 0x80000007.edx, word 7 */ @@ -264,6 +270,7 @@ XEN_CPUFEATURE(BTC_NO, 8*32+29) /*A Hardware not vulnerable to Branch Ty XEN_CPUFEATURE(IBPB_RET, 8*32+30) /*A IBPB clears RSB/RAS too. */ /* Intel-defined CPU features, CPUID level 0x00000007:0.edx, word 9 */ +XEN_CPUFEATURE(SGX_KEYS, 9*32+ 1) /* SGX Attestation Service */ XEN_CPUFEATURE(AVX512_4VNNIW, 9*32+ 2) /* Xeon Phi AVX512 Neural Network Instructions */ XEN_CPUFEATURE(AVX512_4FMAPS, 9*32+ 3) /* Xeon Phi AVX512 Multiply Accumulation Single Precision */ XEN_CPUFEATURE(FSRM, 9*32+ 4) /*A Fast Short REP MOVS */ @@ -276,10 +283,13 @@ XEN_CPUFEATURE(TSX_FORCE_ABORT, 9*32+13) /* MSR_TSX_FORCE_ABORT.RTM_ABORT */ XEN_CPUFEATURE(SERIALIZE, 9*32+14) /*A SERIALIZE insn */ XEN_CPUFEATURE(HYBRID, 9*32+15) /* Heterogeneous platform */ XEN_CPUFEATURE(TSXLDTRK, 9*32+16) /*a TSX load tracking suspend/resume insns */ +XEN_CPUFEATURE(PCONFIG, 9*32+18) /* PCONFIG insn */ XEN_CPUFEATURE(ARCH_LBR, 9*32+19) /* Architectural Last Branch Record */ XEN_CPUFEATURE(CET_IBT, 9*32+20) /* CET - Indirect Branch Tracking */ +XEN_CPUFEATURE(AMX_BF16, 9*32+22) /* Tile computational operations on bfloat16 numbers */ XEN_CPUFEATURE(AVX512_FP16, 9*32+23) /*A AVX512 FP16 instructions */ XEN_CPUFEATURE(AMX_TILE, 9*32+24) /* AMX Tile architecture */ +XEN_CPUFEATURE(AMX_INT8, 9*32+25) /* Tile computational operations on 8-bit integers */ XEN_CPUFEATURE(IBRSB, 9*32+26) /*A IBRS and IBPB support (used by Intel) */ XEN_CPUFEATURE(STIBP, 9*32+27) /*A STIBP */ XEN_CPUFEATURE(L1D_FLUSH, 9*32+28) /*S MSR_FLUSH_CMD and L1D flush. */
Upon running `xen-cpuid -v` on a host machine with Sapphire Rapids within Dom0, there exist unrecognised features. This patch adds these features as macros to the CPU featureset, disabled by default. Signed-off-by: Matthew Barnes <matthew.barnes@cloud.com> --- Changes in v2: - Remove MONITOR / UMONITOR features in MSR_ARCH_CAPS (these will be included properly in a separate patch) - Xen cpufeature label renames - Xen cpufeature comment rewords - Tweak cli flag in commit description --- xen/include/public/arch-x86/cpufeatureset.h | 10 ++++++++++ 1 file changed, 10 insertions(+)