| Message ID | 2bac0ded3456e04b49b48cf0808203e76fc6a622.1743771654.git.teddy.astie@vates.tech (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | [v3,1/2] x86/amd: Add guest support for AMD TCE | expand |
Sorry I forgot to run add_maintainers on this patch series, so this serie got only sent to xen-devel@lists.xenproject.org without the proper CC. Teddy Teddy Astie | Vates XCP-ng Developer XCP-ng & Xen Orchestra - Vates solutions web: https://vates.tech
On 07.04.2025 11:10, Teddy Astie wrote: > AMD Translation Cache Extension is a flag that can be enabled in the EFER MSR to optimize > some TLB flushes. Expose this flag to guest if supported by hardware. This flag can be > used by Linux since version 6.14. > > Only expose this feature to HAP-enabled guests. Guests with shadow paging guests have Nit: double "guests". > their TLB flush operations intercepted and handled separately, without taking account > to this flag. PV guest follows Xen TLB flush behavior. Commit messages want to have their lines limited to like 75 chars, to cover for e.g. "git log" behavior combined with the general 80 chars line length limit. > --- a/CHANGELOG.md > +++ b/CHANGELOG.md > @@ -18,6 +18,7 @@ The format is based on [Keep a Changelog](https://keepachangelog.com/en/1.0.0/) > - Support PCI passthrough for HVM domUs when dom0 is PVH (note SR-IOV > capability usage is not yet supported on PVH dom0). > - Smoke tests for the FreeBSD Xen builds in Cirrus CI. > + - Guest support for AMD Translation Cache Extension feature. This may want to say HVM or even HAP. > --- a/xen/arch/x86/pv/emul-priv-op.c > +++ b/xen/arch/x86/pv/emul-priv-op.c > @@ -857,8 +857,8 @@ static uint64_t guest_efer(const struct domain *d) > { > uint64_t val; > > - /* Hide unknown bits, and unconditionally hide SVME and AIBRSE from guests. */ > - val = read_efer() & EFER_KNOWN_MASK & ~(EFER_SVME | EFER_AIBRSE); > + /* Hide unknown bits, and unconditionally hide SVME, TCE and AIBRSE from guests. */ > + val = read_efer() & EFER_KNOWN_MASK & ~(EFER_SVME | EFER_TCE | EFER_AIBRSE); Nit: Please respect line length limits when extending lines. Jan
On 07.04.2025 11:10, Teddy Astie wrote: > --- a/xen/include/public/arch-x86/cpufeatureset.h > +++ b/xen/include/public/arch-x86/cpufeatureset.h > @@ -170,6 +170,7 @@ XEN_CPUFEATURE(SKINIT, 3*32+12) /* SKINIT/STGI instructions */ > XEN_CPUFEATURE(WDT, 3*32+13) /* Watchdog timer */ > XEN_CPUFEATURE(LWP, 3*32+15) /* Light Weight Profiling */ > XEN_CPUFEATURE(FMA4, 3*32+16) /*A 4 operands MAC instructions */ > +XEN_CPUFEATURE(TCE, 3*32+17) /*H Translation Cache Extension support */ I consider this too limiting; this is a performance hint only, after all, not affecting correctness when ignored if set. A shadow guest is fine to enable TCE if it sees fit. It'll benefit if later migrated to a HAP- capable host. Further a HAP guest is also fine to set this bit even on a TCE-incapable host. It'll benefit when migrated to a TCE-capable one. What we'd need to ensure is that on TCE-incapable hosts only the guest view of EFER has the bit set, while what's in the VMCB for hardware to use hasn't. (Arguably support for this can come later, but the shortcoming would want pointing out imo.) Jan
On 09.04.2025 10:53, Jan Beulich wrote: > On 07.04.2025 11:10, Teddy Astie wrote: >> --- a/xen/include/public/arch-x86/cpufeatureset.h >> +++ b/xen/include/public/arch-x86/cpufeatureset.h >> @@ -170,6 +170,7 @@ XEN_CPUFEATURE(SKINIT, 3*32+12) /* SKINIT/STGI instructions */ >> XEN_CPUFEATURE(WDT, 3*32+13) /* Watchdog timer */ >> XEN_CPUFEATURE(LWP, 3*32+15) /* Light Weight Profiling */ >> XEN_CPUFEATURE(FMA4, 3*32+16) /*A 4 operands MAC instructions */ >> +XEN_CPUFEATURE(TCE, 3*32+17) /*H Translation Cache Extension support */ > > I consider this too limiting; this is a performance hint only, after all, > not affecting correctness when ignored if set. A shadow guest is fine to > enable TCE if it sees fit. It'll benefit if later migrated to a HAP- > capable host. Further to this: From all I can find it doesn't become clear whether INVLPGA acts like INVLPG as to upper-level entries. Implicitly it comes closer to acting like INVLPG with TCE set. Which may be the reason why svm_invlpg() doesn't use INVLPGA. Yet that could change then for guests having TCE set, which means it would become relevant to expose the bit also to shadow guests. Jan
diff --git a/CHANGELOG.md b/CHANGELOG.md index 8f6afa5c85..dbfecefbd4 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -18,6 +18,7 @@ The format is based on [Keep a Changelog](https://keepachangelog.com/en/1.0.0/) - Support PCI passthrough for HVM domUs when dom0 is PVH (note SR-IOV capability usage is not yet supported on PVH dom0). - Smoke tests for the FreeBSD Xen builds in Cirrus CI. + - Guest support for AMD Translation Cache Extension feature. ### Removed diff --git a/xen/arch/x86/hvm/hvm.c b/xen/arch/x86/hvm/hvm.c index 5950f3160f..184357b042 100644 --- a/xen/arch/x86/hvm/hvm.c +++ b/xen/arch/x86/hvm/hvm.c @@ -959,6 +959,9 @@ const char *hvm_efer_valid(const struct vcpu *v, uint64_t value, if ( (value & EFER_FFXSE) && !p->extd.ffxsr ) return "FFXSE without feature"; + if ( (value & EFER_TCE) && !p->extd.tce ) + return "TCE without feature"; + if ( (value & EFER_AIBRSE) && !p->extd.auto_ibrs ) return "AutoIBRS without feature"; diff --git a/xen/arch/x86/include/asm/msr-index.h b/xen/arch/x86/include/asm/msr-index.h index 22d9e76e55..d8576aec1c 100644 --- a/xen/arch/x86/include/asm/msr-index.h +++ b/xen/arch/x86/include/asm/msr-index.h @@ -200,11 +200,12 @@ #define EFER_NXE (_AC(1, ULL) << 11) /* No Execute Enable */ #define EFER_SVME (_AC(1, ULL) << 12) /* Secure Virtual Machine Enable */ #define EFER_FFXSE (_AC(1, ULL) << 14) /* Fast FXSAVE/FXRSTOR */ +#define EFER_TCE (_AC(1, ULL) << 15) /* Translation Cache Extensions */ #define EFER_AIBRSE (_AC(1, ULL) << 21) /* Automatic IBRS Enable */ #define EFER_KNOWN_MASK \ (EFER_SCE | EFER_LME | EFER_LMA | EFER_NXE | EFER_SVME | EFER_FFXSE | \ - EFER_AIBRSE) + EFER_TCE | EFER_AIBRSE) #define MSR_STAR _AC(0xc0000081, U) /* legacy mode SYSCALL target */ #define MSR_LSTAR _AC(0xc0000082, U) /* long mode SYSCALL target */ diff --git a/xen/arch/x86/pv/emul-priv-op.c b/xen/arch/x86/pv/emul-priv-op.c index 70150c2722..531228b2da 100644 --- a/xen/arch/x86/pv/emul-priv-op.c +++ b/xen/arch/x86/pv/emul-priv-op.c @@ -857,8 +857,8 @@ static uint64_t guest_efer(const struct domain *d) { uint64_t val; - /* Hide unknown bits, and unconditionally hide SVME and AIBRSE from guests. */ - val = read_efer() & EFER_KNOWN_MASK & ~(EFER_SVME | EFER_AIBRSE); + /* Hide unknown bits, and unconditionally hide SVME, TCE and AIBRSE from guests. */ + val = read_efer() & EFER_KNOWN_MASK & ~(EFER_SVME | EFER_TCE | EFER_AIBRSE); /* * Hide the 64-bit features from 32-bit guests. SCE has * vendor-dependent behaviour. diff --git a/xen/include/public/arch-x86/cpufeatureset.h b/xen/include/public/arch-x86/cpufeatureset.h index cc6e984a88..8182d2dbed 100644 --- a/xen/include/public/arch-x86/cpufeatureset.h +++ b/xen/include/public/arch-x86/cpufeatureset.h @@ -170,6 +170,7 @@ XEN_CPUFEATURE(SKINIT, 3*32+12) /* SKINIT/STGI instructions */ XEN_CPUFEATURE(WDT, 3*32+13) /* Watchdog timer */ XEN_CPUFEATURE(LWP, 3*32+15) /* Light Weight Profiling */ XEN_CPUFEATURE(FMA4, 3*32+16) /*A 4 operands MAC instructions */ +XEN_CPUFEATURE(TCE, 3*32+17) /*H Translation Cache Extension support */ XEN_CPUFEATURE(NODEID_MSR, 3*32+19) /* NodeId MSR */ XEN_CPUFEATURE(TBM, 3*32+21) /*A trailing bit manipulations */ XEN_CPUFEATURE(TOPOEXT, 3*32+22) /* topology extensions CPUID leafs */
AMD Translation Cache Extension is a flag that can be enabled in the EFER MSR to optimize some TLB flushes. Expose this flag to guest if supported by hardware. Only expose this feature to HAP-enabled guests. Guests with shadow paging guests have their TLB flush operations intercepted and handled separately, without taking account to this flag. PV guest follows Xen TLB flush behavior. Signed-off-by: Teddy Astie <teddy.astie@vates.tech> --- v3: - hide from PV guests - review commit description --- CHANGELOG.md | 1 + xen/arch/x86/hvm/hvm.c | 3 +++ xen/arch/x86/include/asm/msr-index.h | 3 ++- xen/arch/x86/pv/emul-priv-op.c | 4 ++-- xen/include/public/arch-x86/cpufeatureset.h | 1 + 5 files changed, 9 insertions(+), 3 deletions(-)