diff mbox series

x86/APIC: drop 32-bit days remnants

Message ID 362d1e97-c9c4-3d52-be6a-3fcd5fd0a27f@suse.com (mailing list archive)
State New, archived
Headers show
Series x86/APIC: drop 32-bit days remnants | expand

Commit Message

Jan Beulich Jan. 17, 2022, 10:33 a.m. UTC 
Mercury and Neptune were Pentium chipsets - no need to work around their
errata, even more so that the workaround looks fragile.

Also ditch a Pentium-related and stale part of a comment.

Signed-off-by: Jan Beulich <jbeulich@suse.com>

Comments

Andrew Cooper Jan. 20, 2022, 4:11 p.m. UTC | #1 
On 17/01/2022 10:33, Jan Beulich wrote:
> Mercury and Neptune were Pentium chipsets - no need to work around their
> errata, even more so that the workaround looks fragile.
>
> Also ditch a Pentium-related and stale part of a comment.
>
> Signed-off-by: Jan Beulich <jbeulich@suse.com>

Acked-by: Andrew Cooper <andrew.cooper3@citrix.com>

Lets hope we don't have something other than Mercury/Neptune depends on
this.
diff mbox series

Patch

--- a/xen/arch/x86/apic.c
+++ b/xen/arch/x86/apic.c
@@ -1042,11 +1042,6 @@  static void __init wait_8254_wraparound(
     do {
         prev_count = curr_count;
         curr_count = get_8254_timer_count();
-
-        /* workaround for broken Mercury/Neptune */
-        if (prev_count >= curr_count + 0x100)
-            curr_count = get_8254_timer_count();
-        
     } while (prev_count >= curr_count);
 }
 
@@ -1056,9 +1051,6 @@  static void __init wait_8254_wraparound(
  * this function twice on the boot CPU, once with a bogus timeout
  * value, second time for real. The other (noncalibrating) CPUs
  * call this function only once, with the real, calibrated value.
- *
- * We do reads before writes even if unnecessary, to get around the
- * P5 APIC double write bug.
  */
 
 #define APIC_DIVISOR 1